nir,ac/llvm,radv: add nir_intrinsic_load_provoking_vtx_in_prim_amd

For radeonsi which load this from arg.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19166>

src/amd/llvm/ac_nir_to_llvm.c

@@ -3616,6 +3616,7 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
    case nir_intrinsic_load_cull_front_face_enabled_amd:
    case nir_intrinsic_load_cull_small_prim_precision_amd:
    case nir_intrinsic_load_cull_small_primitives_enabled_amd:
+   case nir_intrinsic_load_provoking_vtx_in_prim_amd:
       result = ctx->abi->intrinsic_load(ctx->abi, instr->intrinsic);
       break;
    case nir_intrinsic_load_user_clip_plane:

src/amd/vulkan/radv_nir_lower_abi.c

@@ -280,6 +280,23 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
          replacement = nir_imm_int(b, s->pl_key->ps.num_samples);
       }
       break;
+   case nir_intrinsic_load_provoking_vtx_in_prim_amd: {
+      unsigned provoking_vertex = 0;
+      if (s->pl_key->vs.provoking_vtx_last) {
+         if (stage == MESA_SHADER_VERTEX) {
+            provoking_vertex = radv_get_num_vertices_per_prim(s->pl_key) - 1;
+         } else if (stage == MESA_SHADER_GEOMETRY) {
+            provoking_vertex = b->shader->info.gs.vertices_in - 1;
+         } else {
+            /* TES won't use this intrinsic, because it can get primitive id directly
+             * instead of using this intrinsic to pass primitive id by LDS.
+             */
+            unreachable("load_provoking_vtx_in_prim_amd is only supported in VS and GS");
+         }
+      }
+      replacement = nir_imm_int(b, provoking_vertex);
+      break;
+   }
    default:
       break;
    }

src/compiler/nir/nir_divergence_analysis.c

@@ -189,6 +189,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
    case nir_intrinsic_load_num_vertices_per_primitive_amd:
    case nir_intrinsic_load_streamout_buffer_amd:
    case nir_intrinsic_load_ordered_id_amd:
+   case nir_intrinsic_load_provoking_vtx_in_prim_amd:
       is_divergent = false;
       break;
 

src/compiler/nir/nir_intrinsics.py

@@ -1447,6 +1447,9 @@ system_value("ordered_id_amd", 1)
 # WRITE_MASK = mask for counter channel to update
 intrinsic("ordered_xfb_counter_add_amd", dest_comp=0, src_comp=[1, 0], indices=[WRITE_MASK], bit_sizes=[32])
 
+# Provoking vertex index in a primitive
+system_value("provoking_vtx_in_prim_amd", 1)
+
 # V3D-specific instrinc for tile buffer color reads.
 #
 # The hardware requires that we read the samples and components of a pixel