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ac/nir: add force_vrs to ac_nir_export_position

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Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
This commit is contained in:
Qiang Yu
2023-01-29 09:46:43 +08:00
committed by Marge Bot
parent daa12b1ab1
commit 58988c3239
2 changed files with 14 additions and 2 deletions
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15
src/amd/common/ac_nir.c
View File

@@ -75,6 +75,7 @@ ac_nir_export_position(nir_builder *b,
enum amd_gfx_level gfx_level, enum amd_gfx_level gfx_level,
uint32_t clip_cull_mask, uint32_t clip_cull_mask,
bool no_param_export, bool no_param_export,
bool force_vrs,
uint64_t outputs_written, uint64_t outputs_written,
nir_ssa_def *(*outputs)[4]) nir_ssa_def *(*outputs)[4])
{ {
@@ -119,7 +120,7 @@ ac_nir_export_position(nir_builder *b,
if (!outputs[VARYING_SLOT_VIEWPORT][0]) if (!outputs[VARYING_SLOT_VIEWPORT][0])
outputs_written &= ~VARYING_BIT_VIEWPORT; outputs_written &= ~VARYING_BIT_VIEWPORT;
if (outputs_written & mask) { if ((outputs_written & mask) || force_vrs) {
nir_ssa_def *zero = nir_imm_float(b, 0); nir_ssa_def *zero = nir_imm_float(b, 0);
nir_ssa_def *vec[4] = { zero, zero, zero, zero }; nir_ssa_def *vec[4] = { zero, zero, zero, zero };
unsigned flags = 0; unsigned flags = 0;
@@ -135,8 +136,18 @@ ac_nir_export_position(nir_builder *b,
write_mask |= BITFIELD_BIT(1); write_mask |= BITFIELD_BIT(1);
} }
nir_ssa_def *rates = NULL;
if (outputs_written & VARYING_BIT_PRIMITIVE_SHADING_RATE) { if (outputs_written & VARYING_BIT_PRIMITIVE_SHADING_RATE) {
vec[1] = nir_ior(b, vec[1], outputs[VARYING_SLOT_PRIMITIVE_SHADING_RATE][0]); rates = outputs[VARYING_SLOT_PRIMITIVE_SHADING_RATE][0];
} else if (force_vrs) {
/* If Pos.W != 1 (typical for non-GUI elements), use coarse shading. */
nir_ssa_def *pos_w = nir_channel(b, pos, 3);
nir_ssa_def *cond = nir_fneu(b, pos_w, nir_imm_float(b, 1));
rates = nir_bcsel(b, cond, nir_load_force_vrs_rates_amd(b), nir_imm_int(b, 0));
}
if (rates) {
vec[1] = nir_ior(b, vec[1], rates);
write_mask |= BITFIELD_BIT(1); write_mask |= BITFIELD_BIT(1);
} }

1
src/amd/common/ac_nir.h
View File

@@ -81,6 +81,7 @@ ac_nir_export_position(nir_builder *b,
enum amd_gfx_level gfx_level, enum amd_gfx_level gfx_level,
uint32_t clip_cull_mask, uint32_t clip_cull_mask,
bool no_param_export, bool no_param_export,
bool force_vrs,
uint64_t outputs_written, uint64_t outputs_written,
nir_ssa_def *(*outputs)[4]); nir_ssa_def *(*outputs)[4]);