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intel: Drop compressed_multisample_layout_mask from the compiler keys

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The compiler looks at this key field to determine whether to perform
an MCS fetch for a txf_ms or samples_identical texture message, if a
nir_tex_src_ms_mcs_intel source wasn't provided.  If it isn't set,
it instead uses constant 0 (nothing is compressed).

All of the drivers (iris, crocus, anv, hasvk) unconditionally set this
to ~0 because we don't want to pay for costly shader recompiles (which
can cause nasty stuttering).  Most textures are compressed anyway, and
the hardware ignores the l2dms MCS parameter if MCS is disabled.

The only user was BLORP, which sets the key field based on whether the
texture's aux usage has MCS.  But if it has MCS, it also does the MCS
fetch itself and supplies it directly.  Otherwise, it relies on the
compiler to fill in the 0 value.  But it could easily just provide the
0 value itself in that case and not rely on the compiler at all.

With that fixed, we can just drop the key fields entirely.  We leave
them as padding for now to avoid repacking structures; we won't need
to after the next commits anyway.

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20223>
This commit is contained in:
Kenneth Graunke
2022-12-07 20:20:12 -08:00
committed by Marge Bot
parent 5c62f526a4
commit 584e18863e
10 changed files with 10 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/gallium/drivers/crocus/crocus_program.c
View File

@@ -49,8 +49,7 @@
#include "nir/tgsi_to_nir.h"
#define KEY_INIT_NO_ID() \
.base.tex.swizzles[0 ... BRW_MAX_SAMPLERS - 1] = 0x688, \
.base.tex.compressed_multisample_layout_mask = ~0
.base.tex.swizzles[0 ... BRW_MAX_SAMPLERS - 1] = 0x688
#define KEY_INIT() \
.base.program_string_id = ish->program_id, \
.base.limit_trig_input_range = screen->driconf.limit_trig_input_range, \

1
src/gallium/drivers/iris/iris_program.c
View File

@@ -55,7 +55,6 @@
.base.program_string_id = prog_id, \
.base.limit_trig_input_range = limit_trig_input, \
.base.tex.swizzles[0 ... BRW_MAX_SAMPLERS - 1] = 0x688, \
.base.tex.compressed_multisample_layout_mask = ~0, \
.base.tex.msaa_16 = (gen >= 9 ? ~0 : 0)
struct iris_threaded_compile_job {

12
src/intel/blorp/blorp_blit.c
View File

@@ -217,8 +217,7 @@ blorp_nir_txf_ms(nir_builder *b, struct brw_blorp_blit_vars *v,
nir_ssa_def *pos, nir_ssa_def *mcs, nir_alu_type dst_type)
{
nir_tex_instr *tex =
blorp_create_nir_tex_instr(b, v, nir_texop_txf_ms, pos,
mcs != NULL ? 3 : 2, dst_type);
blorp_create_nir_tex_instr(b, v, nir_texop_txf_ms, pos, 3, dst_type);
tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
@@ -230,10 +229,11 @@ blorp_nir_txf_ms(nir_builder *b, struct brw_blorp_blit_vars *v,
tex->src[1].src = nir_src_for_ssa(nir_channel(b, pos, 2));
}
if (mcs) {
if (!mcs)
mcs = nir_imm_zero(b, 4, 32);
tex->src[2].src_type = nir_tex_src_ms_mcs_intel;
tex->src[2].src = nir_src_for_ssa(mcs);
}
nir_builder_instr_insert(b, &tex->instr);
@@ -1527,8 +1527,6 @@ brw_blorp_get_blit_kernel_fs(struct blorp_batch *batch,
struct brw_wm_prog_key wm_key;
brw_blorp_init_wm_prog_key(&wm_key);
wm_key.base.tex.compressed_multisample_layout_mask =
isl_aux_usage_has_mcs(key->tex_aux_usage);
wm_key.base.tex.msaa_16 = key->tex_samples == 16;
wm_key.multisample_fbo = key->rt_samples > 1;
@@ -1569,8 +1567,6 @@ brw_blorp_get_blit_kernel_cs(struct blorp_batch *batch,
struct brw_cs_prog_key cs_key;
brw_blorp_init_cs_prog_key(&cs_key);
cs_key.base.tex.compressed_multisample_layout_mask =
prog_key->tex_aux_usage == ISL_AUX_USAGE_MCS;
cs_key.base.tex.msaa_16 = prog_key->tex_samples == 16;
assert(prog_key->rt_samples == 1);

1
src/intel/blorp/blorp_clear.c
View File

@@ -1371,7 +1371,6 @@ blorp_params_get_mcs_partial_resolve_kernel(struct blorp_batch *batch,
struct brw_wm_prog_key wm_key;
brw_blorp_init_wm_prog_key(&wm_key);
wm_key.base.tex.compressed_multisample_layout_mask = 1;
wm_key.base.tex.msaa_16 = blorp_key.num_samples == 16;
wm_key.multisample_fbo = true;

5
src/intel/compiler/brw_compiler.h
View File

@@ -199,10 +199,7 @@ struct brw_sampler_prog_key_data {
*/
uint32_t gather_channel_quirk_mask;
/**
* Whether this sampler uses the compressed multisample surface layout.
*/
uint32_t compressed_multisample_layout_mask;
uint32_t padding;
/**
* Whether this sampler is using 16x multisampling. If so fetching from

2
src/intel/compiler/brw_debug_recompile.c
View File

@@ -63,8 +63,6 @@ debug_sampler_recompile(const struct brw_compiler *c, void *log,
bool found = false;
found |= check("gather channel quirk", gather_channel_quirk_mask);
found |= check("compressed multisample layout",
compressed_multisample_layout_mask);
found |= check("16x msaa", msaa_16);
found |= check("y_uv image bound", y_uv_image_mask);
found |= check("y_u_v image bound", y_u_v_image_mask);

3
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -6397,8 +6397,7 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
if (srcs[TEX_LOGICAL_SRC_MCS].file == BAD_FILE &&
(instr->op == nir_texop_txf_ms ||
instr->op == nir_texop_samples_identical)) {
if (devinfo->ver >= 7 &&
key_tex->compressed_multisample_layout_mask & (1 << texture)) {
if (devinfo->ver >= 7) {
srcs[TEX_LOGICAL_SRC_MCS] =
emit_mcs_fetch(srcs[TEX_LOGICAL_SRC_COORDINATE],
instr->coord_components,

3
src/intel/compiler/brw_vec4_nir.cpp
View File

@@ -2071,8 +2071,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
if (instr->op == nir_texop_txf_ms ||
instr->op == nir_texop_samples_identical) {
assert(coord_type != NULL);
if (devinfo->ver >= 7 &&
key_tex->compressed_multisample_layout_mask & (1 << texture)) {
if (devinfo->ver >= 7) {
mcs = emit_mcs_fetch(coord_type, coordinate, texture_reg);
} else {
mcs = brw_imm_ud(0u);

8
src/intel/vulkan/anv_pipeline.c
View File

@@ -416,14 +416,6 @@ static void
populate_sampler_prog_key(const struct intel_device_info *devinfo,
struct brw_sampler_prog_key_data *key)
{
/* Almost all multisampled textures are compressed. The only time when we
* don't compress a multisampled texture is for 16x MSAA with a surface
* width greater than 8k which is a bit of an edge case. Since the sampler
* just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
* to tell the compiler to always assume compression.
*/
key->compressed_multisample_layout_mask = ~0;
/* SkyLake added support for 16x MSAA. With this came a new message for
* reading from a 16x MSAA surface with compression. The new message was
* needed because now the MCS data is 64 bits instead of 32 or lower as is

8
src/intel/vulkan_hasvk/anv_pipeline.c
View File

@@ -258,14 +258,6 @@ static void
populate_sampler_prog_key(const struct intel_device_info *devinfo,
struct brw_sampler_prog_key_data *key)
{
/* Almost all multisampled textures are compressed. The only time when we
* don't compress a multisampled texture is for 16x MSAA with a surface
* width greater than 8k which is a bit of an edge case. Since the sampler
* just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
* to tell the compiler to always assume compression.
*/
key->compressed_multisample_layout_mask = ~0;
/* SkyLake added support for 16x MSAA. With this came a new message for
* reading from a 16x MSAA surface with compression. The new message was
* needed because now the MCS data is 64 bits instead of 32 or lower as is