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radv: emit PA_SU_POINT_{SIZE,MINMAX} in si_emit_config()

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These registers don't change during the lifetime of the
command buffer, there is no need to re-emit them when
binding a new pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
2017-10-06 15:39:00 +02:00
parent aab1537568
commit 5848565ee3
2 changed files with 15 additions and 16 deletions
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16
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -488,13 +488,6 @@ radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2); radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
} }
/* 12.4 fixed-point */
static unsigned radv_pack_float_12p4(float x)
{
return x <= 0 ? 0 :
x >= 4096 ? 0xffff : x * 16;
}
struct ac_userdata_info * struct ac_userdata_info *
radv_lookup_user_sgpr(struct radv_pipeline *pipeline, radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
gl_shader_stage stage, gl_shader_stage stage,
@@ -588,19 +581,10 @@ radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL, radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
raster->pa_cl_clip_cntl); raster->pa_cl_clip_cntl);
radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0, radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
raster->spi_interp_control); raster->spi_interp_control);
radeon_set_context_reg_seq(cmd_buffer->cs, R_028A00_PA_SU_POINT_SIZE, 2);
unsigned tmp = (unsigned)(1.0 * 8.0);
radeon_emit(cmd_buffer->cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
radeon_emit(cmd_buffer->cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); /* R_028A04_PA_SU_POINT_MINMAX */
radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL, radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
raster->pa_su_vtx_cntl); raster->pa_su_vtx_cntl);
radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL, radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
raster->pa_su_sc_mode_cntl); raster->pa_su_sc_mode_cntl);
} }

15
src/amd/vulkan/si_cmd_buffer.c
View File

@@ -216,6 +216,13 @@ si_init_compute(struct radv_cmd_buffer *cmd_buffer)
si_emit_compute(physical_device, cmd_buffer->cs); si_emit_compute(physical_device, cmd_buffer->cs);
} }
/* 12.4 fixed-point */
static unsigned radv_pack_float_12p4(float x)
{
return x <= 0 ? 0 :
x >= 4096 ? 0xffff : x * 16;
}
static void static void
si_emit_config(struct radv_physical_device *physical_device, si_emit_config(struct radv_physical_device *physical_device,
struct radeon_winsys_cs *cs) struct radeon_winsys_cs *cs)
@@ -486,6 +493,14 @@ si_emit_config(struct radv_physical_device *physical_device,
S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1)); S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0); radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
} }
unsigned tmp = (unsigned)(1.0 * 8.0);
radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1);
radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1);
radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) |
S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2)));
si_emit_compute(physical_device, cs); si_emit_compute(physical_device, cs);
} }