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intel/compiler: don't use byte operands for src1 on ICL

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The simulator complains about using byte operands, we also have
documentation telling us.

Note that add operations on bytes seems to work fine on HW (like ADD).
Using dwords operands with CMP & SEL fixes the following tests :

   dEQP-VK.spirv_assembly.type.vec*.i8.*

v2: Drop the GLK changes (Matt)
    Add validator tests (Matt)

v3: Drop GLK ref (Matt)
    Don't mix float/integer in MAD (Matt)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> (v1)
Reviewed-by: Matt Turner <mattst88@gmail.com>
BSpec: 3017
Cc: <mesa-stable@lists.freedesktop.org>
This commit is contained in:
Lionel Landwerlin
2019-06-19 05:09:35 -07:00
parent 500b45a98a
commit 5847de6e9a
4 changed files with 192 additions and 20 deletions
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38
src/intel/compiler/brw_fs_builder.h
View File

@@ -322,10 +322,11 @@ namespace brw {
case SHADER_OPCODE_INT_REMAINDER:
return emit(instruction(opcode, dispatch_width(), dst,
fix_math_operand(src0),
fix_math_operand(src1)));
fix_math_operand(fix_byte_src(src1))));
default:
return emit(instruction(opcode, dispatch_width(), dst, src0, src1));
return emit(instruction(opcode, dispatch_width(), dst,
src0, fix_byte_src(src1)));
}
}
@@ -344,12 +345,12 @@ namespace brw {
case BRW_OPCODE_LRP:
return emit(instruction(opcode, dispatch_width(), dst,
fix_3src_operand(src0),
fix_3src_operand(src1),
fix_3src_operand(src2)));
fix_3src_operand(fix_byte_src(src1)),
fix_3src_operand(fix_byte_src(src2))));
default:
return emit(instruction(opcode, dispatch_width(), dst,
src0, src1, src2));
src0, fix_byte_src(src1), fix_byte_src(src2)));
}
}
@@ -399,8 +400,11 @@ namespace brw {
{
assert(mod == BRW_CONDITIONAL_GE || mod == BRW_CONDITIONAL_L);
return set_condmod(mod, SEL(dst, fix_unsigned_negate(src0),
fix_unsigned_negate(src1)));
/* In some cases we can't have bytes as operand for src1, so use the
* same type for both operand.
*/
return set_condmod(mod, SEL(dst, fix_unsigned_negate(fix_byte_src(src0)),
fix_unsigned_negate(fix_byte_src(src1))));
}
/**
@@ -657,8 +661,8 @@ namespace brw {
emit(BRW_OPCODE_CSEL,
retype(dst, BRW_REGISTER_TYPE_F),
retype(src0, BRW_REGISTER_TYPE_F),
retype(src1, BRW_REGISTER_TYPE_F),
src2));
retype(fix_byte_src(src1), BRW_REGISTER_TYPE_F),
fix_byte_src(src2)));
}
/**
@@ -719,6 +723,22 @@ namespace brw {
backend_shader *shader;
/**
* Byte sized operands are not supported for src1 on Gen11+.
*/
src_reg
fix_byte_src(const src_reg &src) const
{
if ((shader->devinfo->gen < 11 && !shader->devinfo->is_geminilake) ||
type_sz(src.type) != 1)
return src;
dst_reg temp = vgrf(src.type == BRW_REGISTER_TYPE_UB ?
BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_D);
MOV(temp, src);
return src_reg(temp);
}
private:
/**
* Workaround for negation of UD registers. See comment in