intel/brw: Introduce a new SSA-based copy propagation pass
(Quite a few of the restrictions here are ported from the old pass.) Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28666>
This commit is contained in:
Kenneth Graunke
committed by
Marge Bot
Marge Bot
parent
9690bd369d
commit
580e1c592d
@@ -671,6 +671,7 @@ bool brw_fs_opt_cmod_propagation(fs_visitor &s);
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bool brw_fs_opt_combine_constants(fs_visitor &s);
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bool brw_fs_opt_compact_virtual_grfs(fs_visitor &s);
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bool brw_fs_opt_copy_propagation(fs_visitor &s);
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bool brw_fs_opt_copy_propagation_defs(fs_visitor &s);
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bool brw_fs_opt_cse_defs(fs_visitor &s);
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bool brw_fs_opt_dead_code_eliminate(fs_visitor &s);
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bool brw_fs_opt_dead_control_flow_eliminate(fs_visitor &s);
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@@ -1482,3 +1482,375 @@ brw_fs_opt_copy_propagation(fs_visitor &s)
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return progress;
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}
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static bool
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try_copy_propagate_def(const brw_compiler *compiler,
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const brw::simple_allocator &alloc,
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fs_inst *def, const fs_reg &val,
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fs_inst *inst, int arg,
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uint8_t max_polygons)
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{
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const struct intel_device_info *devinfo = compiler->devinfo;
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assert(val.file != BAD_FILE);
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/* We can't generally copy-propagate UD negations because we can end up
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* accessing the resulting values as signed integers instead.
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*/
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if (val.negate && val.type == BRW_TYPE_UD)
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return false;
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/* Bail if the instruction type is larger than the execution type of the
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* copy, what implies that each channel is reading multiple channels of the
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* destination of the copy, and simply replacing the sources would give a
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* program with different semantics.
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*/
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if (inst->opcode != BRW_OPCODE_MOV &&
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brw_type_size_bits(def->dst.type) <
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brw_type_size_bits(inst->src[arg].type))
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return false;
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const bool has_source_modifiers = val.abs || val.negate;
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if (has_source_modifiers) {
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if (is_logic_op(inst->opcode) || !inst->can_do_source_mods(devinfo))
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return false;
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/* Since semantics of source modifiers are type-dependent we need to
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* ensure that the meaning of the instruction remains the same if we
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* change the type. If the sizes of the types are different the new
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* instruction will read a different amount of data than the original
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* and the semantics will always be different.
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*/
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if (def->dst.type != inst->src[arg].type &&
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(!inst->can_change_types() ||
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brw_type_size_bits(def->dst.type) !=
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brw_type_size_bits(inst->src[arg].type)))
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return false;
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}
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/* Send messages with EOT set are restricted to use g112-g127 (and we
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* sometimes need g127 for other purposes), so avoid copy propagating
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* anything that would make it impossible to satisfy that restriction.
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*/
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if (inst->eot) {
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/* Don't propagate things that are already pinned. */
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if (val.file != VGRF)
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return false;
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/* We might be propagating from a large register, while the SEND only
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* is reading a portion of it (say the .A channel in an RGBA value).
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* We need to pin both split SEND sources in g112-g126/127, so only
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* allow this if the registers aren't too large.
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*/
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if (inst->opcode == SHADER_OPCODE_SEND && inst->sources >= 4 &&
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val.file == VGRF) {
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int other_src = arg == 2 ? 3 : 2;
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unsigned other_size = inst->src[other_src].file == VGRF ?
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alloc.sizes[inst->src[other_src].nr] :
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inst->size_read(other_src);
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unsigned prop_src_size = alloc.sizes[val.nr];
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if (other_size + prop_src_size > 15)
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return false;
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}
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}
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/* Reject cases that would violate register regioning restrictions. */
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if ((val.file == UNIFORM || !val.is_contiguous()) &&
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(inst->is_send_from_grf() || inst->uses_indirect_addressing())) {
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return false;
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}
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/* Some instructions implemented in the generator backend, such as
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* derivatives, assume that their operands are packed so we can't
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* generally propagate strided regions to them.
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*/
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const unsigned entry_stride = val.file == FIXED_GRF ? 1 : val.stride;
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if (instruction_requires_packed_data(inst) && entry_stride != 1)
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return false;
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const brw_reg_type dst_type = (has_source_modifiers &&
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def->dst.type != inst->src[arg].type) ?
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def->dst.type : inst->dst.type;
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/* Bail if the result of composing both strides would exceed the
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* hardware limit.
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*/
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if (!can_take_stride(inst, dst_type, arg,
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entry_stride * inst->src[arg].stride,
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compiler))
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return false;
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/* Bail if the source FIXED_GRF region of the copy cannot be trivially
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* composed with the source region of the instruction -- E.g. because the
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* copy uses some extended stride greater than 4 not supported natively by
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* the hardware as a horizontal stride, or because instruction compression
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* could require us to use a vertical stride shorter than a GRF.
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*/
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if (val.file == FIXED_GRF &&
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(inst->src[arg].stride > 4 ||
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inst->dst.component_size(inst->exec_size) >
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inst->src[arg].component_size(inst->exec_size)))
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return false;
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/* Bail if the result of composing both strides cannot be expressed
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* as another stride. This avoids, for example, trying to transform
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* this:
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*
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* MOV (8) rX<1>UD rY<0;1,0>UD
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* FOO (8) ... rX<8;8,1>UW
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*
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* into this:
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*
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* FOO (8) ... rY<0;1,0>UW
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*
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* Which would have different semantics.
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*/
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if (entry_stride != 1 &&
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(inst->src[arg].stride *
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brw_type_size_bytes(inst->src[arg].type)) % brw_type_size_bytes(val.type) != 0)
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return false;
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/* From the Cherry Trail/Braswell PRMs, Volume 7: 3D Media GPGPU:
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* EU Overview
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* Register Region Restrictions
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* Special Requirements for Handling Double Precision Data Types :
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*
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* "When source or destination datatype is 64b or operation is integer
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* DWord multiply, regioning in Align1 must follow these rules:
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*
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* 1. Source and Destination horizontal stride must be aligned to the
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* same qword.
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* 2. Regioning must ensure Src.Vstride = Src.Width * Src.Hstride.
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* 3. Source and Destination offset must be the same, except the case
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* of scalar source."
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*
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* Most of this is already checked in can_take_stride(), we're only left
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* with checking 3.
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*/
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if (has_dst_aligned_region_restriction(devinfo, inst, dst_type) &&
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entry_stride != 0 &&
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(reg_offset(inst->dst) % (REG_SIZE * reg_unit(devinfo))) != (reg_offset(val) % (REG_SIZE * reg_unit(devinfo))))
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return false;
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/* The <8;8,0> regions used for FS attributes in multipolygon
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* dispatch mode could violate regioning restrictions, don't copy
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* propagate them in such cases.
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*/
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if (max_polygons > 1 && val.file == ATTR &&
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(has_dst_aligned_region_restriction(devinfo, inst, dst_type) ||
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instruction_requires_packed_data(inst) ||
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(inst->is_3src(compiler) && arg == 2) ||
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def->dst.type != inst->src[arg].type))
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return false;
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/* Fold the copy into the instruction consuming it. */
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inst->src[arg].file = val.file;
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inst->src[arg].nr = val.nr;
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inst->src[arg].subnr = val.subnr;
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inst->src[arg].offset = val.offset;
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/* Compose the strides of both regions. */
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if (val.file == FIXED_GRF) {
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if (inst->src[arg].stride) {
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const unsigned orig_width = 1 << val.width;
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const unsigned reg_width =
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REG_SIZE / (brw_type_size_bytes(inst->src[arg].type) *
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inst->src[arg].stride);
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inst->src[arg].width = cvt(MIN2(orig_width, reg_width)) - 1;
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inst->src[arg].hstride = cvt(inst->src[arg].stride);
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inst->src[arg].vstride = inst->src[arg].hstride + inst->src[arg].width;
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} else {
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inst->src[arg].vstride = inst->src[arg].hstride =
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inst->src[arg].width = 0;
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}
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inst->src[arg].stride = 1;
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/* Hopefully no Align16 around here... */
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assert(val.swizzle == BRW_SWIZZLE_XYZW);
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inst->src[arg].swizzle = val.swizzle;
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} else {
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inst->src[arg].stride *= val.stride;
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}
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/* Handle NoMask cases where the def replicates a small scalar to a number
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* of channels, but the use is a lower SIMD width but larger type, so each
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* invocation reads multiple channels worth of data, e.g.
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*
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* mov(16) vgrf1:UW, u0<0>:UW NoMask
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* mov(8) vgrf2:UD, vgrf1:UD NoMask group0
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*
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* In this case, we should just use the scalar's type.
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*/
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if (val.stride == 0 &&
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inst->opcode == BRW_OPCODE_MOV &&
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inst->force_writemask_all && def->force_writemask_all &&
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inst->exec_size < def->exec_size &&
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(inst->exec_size * brw_type_size_bytes(inst->src[arg].type) ==
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def->exec_size * brw_type_size_bytes(val.type))) {
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inst->src[arg].type = val.type;
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inst->dst.type = val.type;
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inst->exec_size = def->exec_size;
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}
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if (has_source_modifiers) {
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if (def->dst.type != inst->src[arg].type) {
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/* We are propagating source modifiers from a MOV with a different
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* type. If we got here, then we can just change the source and
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* destination types of the instruction and keep going.
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*/
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for (int i = 0; i < inst->sources; i++) {
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inst->src[i].type = def->dst.type;
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}
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inst->dst.type = def->dst.type;
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}
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if (!inst->src[arg].abs) {
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inst->src[arg].abs = val.abs;
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inst->src[arg].negate ^= val.negate;
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}
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}
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return true;
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}
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static bool
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try_constant_propagate_def(fs_inst *def, fs_reg val, fs_inst *inst, int arg)
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{
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/* Bail if inst is reading more than a single vector component of entry */
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if (inst->size_read(arg) > def->dst.component_size(inst->exec_size))
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return false;
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return try_constant_propagate_value(val, def->dst.type, inst, arg);
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}
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/**
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* Handle cases like UW subreads of a UD immediate, with an offset.
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*/
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static fs_reg
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extract_imm(fs_reg val, brw_reg_type type, unsigned offset)
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{
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assert(val.file == IMM);
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const unsigned bitsize = brw_type_size_bits(type);
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if (offset == 0 || bitsize == brw_type_size_bits(val.type))
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return val;
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assert(bitsize < brw_type_size_bits(val.type));
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switch (val.type) {
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case BRW_TYPE_UD:
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val.ud = (val.ud >> (bitsize * offset)) & ((1u << bitsize) - 1);
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break;
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case BRW_TYPE_D:
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val.d = (val.d << (bitsize * (32/bitsize - 1 - offset))) >> ((32/bitsize - 1) * bitsize);
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break;
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default:
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return fs_reg();
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}
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return val;
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}
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static fs_reg
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find_value_for_offset(fs_inst *def, const fs_reg &src, unsigned src_size)
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{
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fs_reg val;
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switch (def->opcode) {
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case BRW_OPCODE_MOV:
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if (def->dst.type == def->src[0].type && def->src[0].stride <= 1) {
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val = def->src[0];
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unsigned rel_offset = src.offset - def->dst.offset;
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if (val.stride == 0)
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rel_offset %= brw_type_size_bytes(def->dst.type);
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if (val.file == IMM)
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val = extract_imm(val, src.type, rel_offset);
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else
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val = byte_offset(def->src[0], rel_offset);
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}
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break;
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case SHADER_OPCODE_LOAD_PAYLOAD: {
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unsigned offset = 0;
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for (int i = def->header_size; i < def->sources; i++) {
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const unsigned splat = def->src[i].stride == 0 ? def->exec_size : 1;
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if (offset == src.offset) {
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if (def->dst.type == def->src[i].type &&
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def->src[i].stride <= 1 &&
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def->src[i].component_size(def->exec_size) * splat == src_size)
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val = def->src[i];
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break;
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}
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offset += def->exec_size * brw_type_size_bytes(def->src[i].type);
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}
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break;
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}
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default:
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break;
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}
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return val;
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}
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bool
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brw_fs_opt_copy_propagation_defs(fs_visitor &s)
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{
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const brw::def_analysis &defs = s.def_analysis.require();
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bool progress = false;
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foreach_block_and_inst(block, fs_inst, inst, s.cfg) {
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/* Try propagating into this instruction. */
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bool instruction_progress = false;
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for (int i = inst->sources - 1; i >= 0; i--) {
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fs_inst *def = defs.get(inst->src[i]);
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if (!def || def->saturate)
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continue;
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if (def->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
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if (inst->size_read(i) == def->size_written &&
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def->src[0].file != BAD_FILE && def->src[0].file != IMM &&
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is_identity_payload(def->src[0].file, def)) {
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instruction_progress |=
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try_copy_propagate_def(s.compiler, s.alloc, def, def->src[0],
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inst, i, s.max_polygons);
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continue;
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}
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}
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fs_reg val =
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find_value_for_offset(def, inst->src[i], inst->size_read(i));
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if (val.file == IMM) {
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instruction_progress |=
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try_constant_propagate_def(def, val, inst, i);
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} else if (val.file == VGRF ||
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val.file == ATTR || val.file == UNIFORM ||
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(val.file == FIXED_GRF && val.is_contiguous())) {
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instruction_progress |=
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try_copy_propagate_def(s.compiler, s.alloc, def, val, inst, i,
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s.max_polygons);
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}
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}
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if (instruction_progress) {
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progress = true;
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commute_immediates(inst);
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}
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}
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if (progress) {
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s.invalidate_analysis(DEPENDENCY_INSTRUCTION_DATA_FLOW |
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DEPENDENCY_INSTRUCTION_DETAIL);
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}
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return progress;
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}
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