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radv: pass a radv_physical_device to radv_use_llvm_for_stage()

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28519>
This commit is contained in:
Samuel Pitoiset
2024-04-01 20:12:01 +02:00
committed by Marge Bot
parent 1a48e57a3d
commit 57dd6691df
5 changed files with 18 additions and 15 deletions
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13
src/amd/vulkan/radv_pipeline.c
View File

@@ -500,7 +500,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
NIR_PASS(_, stage->nir, nir_opt_non_uniform_access);
}
if (!radv_use_llvm_for_stage(device, stage->stage)) {
if (!radv_use_llvm_for_stage(pdev, stage->stage)) {
nir_lower_non_uniform_access_options options = {
.types = lower_non_uniform_access_types,
.callback = &non_uniform_access_callback,
@@ -552,7 +552,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
nir_shader_gather_info(stage->nir, nir_shader_get_entrypoint(stage->nir));
bool fix_derivs_in_divergent_cf =
stage->stage == MESA_SHADER_FRAGMENT && !radv_use_llvm_for_stage(device, stage->stage);
stage->stage == MESA_SHADER_FRAGMENT && !radv_use_llvm_for_stage(pdev, stage->stage);
if (fix_derivs_in_divergent_cf) {
NIR_PASS(_, stage->nir, nir_convert_to_lcssa, true, true);
nir_divergence_analysis(stage->nir);
@@ -621,7 +621,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
ac_nir_lower_ps_options options = {
.gfx_level = gfx_level,
.family = pdev->info.family,
.use_aco = !radv_use_llvm_for_stage(device, stage->stage),
.use_aco = !radv_use_llvm_for_stage(pdev, stage->stage),
.uses_discard = true,
.alpha_func = COMPARE_FUNC_ALWAYS,
.no_color_export = stage->info.has_epilog,
@@ -671,7 +671,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
.allow_fp16 = gfx_level >= GFX9,
});
if (radv_use_llvm_for_stage(device, stage->stage))
if (radv_use_llvm_for_stage(pdev, stage->stage))
NIR_PASS_V(stage->nir, nir_lower_io_to_scalar, nir_var_mem_global, NULL, NULL);
NIR_PASS(_, stage->nir, ac_nir_lower_global_access);
@@ -715,7 +715,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat
.fold_tex_dest_types = nir_type_float,
.fold_image_dest_types = nir_type_float,
.fold_image_store_data = true,
.fold_image_srcs = !radv_use_llvm_for_stage(device, stage->stage),
.fold_image_srcs = !radv_use_llvm_for_stage(pdev, stage->stage),
.fold_srcs_options_count = separate_g16 ? 2 : 1,
.fold_srcs_options = fold_srcs_options,
};
@@ -1071,6 +1071,7 @@ radv_GetPipelineExecutableInternalRepresentationsKHR(
{
RADV_FROM_HANDLE(radv_device, device, _device);
RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
const struct radv_physical_device *pdev = radv_device_physical(device);
gl_shader_stage stage;
struct radv_shader *shader =
radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
@@ -1092,7 +1093,7 @@ radv_GetPipelineExecutableInternalRepresentationsKHR(
/* backend IR */
if (p < end) {
p->isText = true;
if (radv_use_llvm_for_stage(device, stage)) {
if (radv_use_llvm_for_stage(pdev, stage)) {
desc_copy(p->name, "LLVM IR");
desc_copy(p->description, "The LLVM IR after some optimizations");
} else {

3
src/amd/vulkan/radv_private.h
View File

@@ -3758,9 +3758,8 @@ void radv_video_get_profile_alignments(struct radv_physical_device *pdev, const
* specific shader stage (developers only).
*/
static inline bool
radv_use_llvm_for_stage(const struct radv_device *device, UNUSED gl_shader_stage stage)
radv_use_llvm_for_stage(const struct radv_physical_device *pdev, UNUSED gl_shader_stage stage)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
return pdev->use_llvm;
}

10
src/amd/vulkan/radv_shader.c
View File

@@ -611,7 +611,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st
bool gfx7minus = pdev->info.gfx_level <= GFX7;
bool has_inverse_ballot = true;
#if LLVM_AVAILABLE
has_inverse_ballot = !radv_use_llvm_for_stage(device, nir->info.stage) || LLVM_VERSION_MAJOR >= 17;
has_inverse_ballot = !radv_use_llvm_for_stage(pdev, nir->info.stage) || LLVM_VERSION_MAJOR >= 17;
#endif
NIR_PASS(_, nir, nir_lower_subgroups,
@@ -622,7 +622,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st
.lower_to_scalar = 1,
.lower_subgroup_masks = 1,
.lower_relative_shuffle = 1,
.lower_rotate_to_shuffle = radv_use_llvm_for_stage(device, nir->info.stage),
.lower_rotate_to_shuffle = radv_use_llvm_for_stage(pdev, nir->info.stage),
.lower_shuffle_to_32bit = 1,
.lower_vote_eq = 1,
.lower_vote_bool_eq = 1,
@@ -2510,10 +2510,12 @@ shader_compile(struct radv_device *device, struct nir_shader *const *shaders, in
struct radv_shader_binary *binary = NULL;
#if LLVM_AVAILABLE
if (radv_use_llvm_for_stage(device, stage) || options->dump_shader || options->record_ir)
const struct radv_physical_device *pdev = radv_device_physical(device);
if (radv_use_llvm_for_stage(pdev, stage) || options->dump_shader || options->record_ir)
ac_init_llvm_once();
if (radv_use_llvm_for_stage(device, stage)) {
if (radv_use_llvm_for_stage(pdev, stage)) {
llvm_compile_shader(options, info, shader_count, shaders, &binary, args);
#else
if (false) {

5
src/amd/vulkan/radv_shader_args.c
View File

@@ -312,10 +312,11 @@ declare_ngg_sgprs(const struct radv_shader_info *info, struct radv_shader_args *
static void
radv_init_shader_args(const struct radv_device *device, gl_shader_stage stage, struct radv_shader_args *args)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
memset(args, 0, sizeof(*args));
args->explicit_scratch_args = !radv_use_llvm_for_stage(device, stage);
args->remap_spi_ps_input = !radv_use_llvm_for_stage(device, stage);
args->explicit_scratch_args = !radv_use_llvm_for_stage(pdev, stage);
args->remap_spi_ps_input = !radv_use_llvm_for_stage(pdev, stage);
args->load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr;
for (int i = 0; i < MAX_SETS; i++)

2
src/amd/vulkan/radv_shader_info.c
View File

@@ -1802,7 +1802,7 @@ radv_link_shaders_info(struct radv_device *device, struct radv_shader_stage *pro
ac_compute_lshs_workgroup_size(pdev->info.gfx_level, MESA_SHADER_VERTEX, tcs_stage->info.num_tess_patches,
gfx_state->ts.patch_control_points, tcs_stage->info.tcs.tcs_vertices_out);
if (!radv_use_llvm_for_stage(device, MESA_SHADER_VERTEX)) {
if (!radv_use_llvm_for_stage(pdev, MESA_SHADER_VERTEX)) {
/* When the number of TCS input and output vertices are the same (typically 3):
* - There is an equal amount of LS and HS invocations
* - In case of merged LSHS shaders, the LS and HS halves of the shader always process