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i965: Support importing R8 and GR88 dma_bufs

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EGL_EXT_image_dma_buf_import now supports those formats.

Tests:
  - Tested by Piglit ext_image_dma_buf_import-transcode-nv12-as-r8-gr88.
  - Tested by Peter in Kodi/XBMC to obtain 60fps NV12 transcode at 4K.

Tested-by: Peter Frühberger <peter.fruehberger@gmail.com>
Signed-off-by: Chad Versace <chad.versace@intel.com>
This commit is contained in:
Chad Versace
2015-06-23 15:48:40 -07:00
parent fd865d56d2
commit 56f1f47eda
2 changed files with 13 additions and 2 deletions
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9
include/GL/internal/dri_interface.h
View File

@@ -1094,12 +1094,15 @@ struct __DRIdri2ExtensionRec {
/** /**
* Four CC formats that matches with WL_DRM_FORMAT_* from wayland_drm.h * Four CC formats that matches with WL_DRM_FORMAT_* from wayland_drm.h,
* and GBM_FORMAT_* from gbm.h, used with createImageFromNames. * GBM_FORMAT_* from gbm.h, and DRM_FORMAT_* from drm_fourcc.h. Used with
* createImageFromNames.
* *
* \since 5 * \since 5
*/ */
#define __DRI_IMAGE_FOURCC_R8 0x20203852
#define __DRI_IMAGE_FOURCC_GR88 0x38385247
#define __DRI_IMAGE_FOURCC_RGB565 0x36314752 #define __DRI_IMAGE_FOURCC_RGB565 0x36314752
#define __DRI_IMAGE_FOURCC_ARGB8888 0x34325241 #define __DRI_IMAGE_FOURCC_ARGB8888 0x34325241
#define __DRI_IMAGE_FOURCC_XRGB8888 0x34325258 #define __DRI_IMAGE_FOURCC_XRGB8888 0x34325258
@@ -1134,6 +1137,8 @@ struct __DRIdri2ExtensionRec {
#define __DRI_IMAGE_COMPONENTS_Y_U_V 0x3003 #define __DRI_IMAGE_COMPONENTS_Y_U_V 0x3003
#define __DRI_IMAGE_COMPONENTS_Y_UV 0x3004 #define __DRI_IMAGE_COMPONENTS_Y_UV 0x3004
#define __DRI_IMAGE_COMPONENTS_Y_XUXV 0x3005 #define __DRI_IMAGE_COMPONENTS_Y_XUXV 0x3005
#define __DRI_IMAGE_COMPONENTS_R 0x3006
#define __DRI_IMAGE_COMPONENTS_RG 0x3007
/** /**

6
src/mesa/drivers/dri/i965/intel_screen.c
View File

@@ -229,6 +229,12 @@ static struct intel_image_format intel_image_formats[] = {
{ __DRI_IMAGE_FOURCC_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1, { __DRI_IMAGE_FOURCC_RGB565, __DRI_IMAGE_COMPONENTS_RGB, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } }, { { 0, 0, 0, __DRI_IMAGE_FORMAT_RGB565, 2 } } },
{ __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
{ __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } },
{ __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3, { __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },