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radeon/r200: drop remains of r300/r600 support along with old drm 1.x kernel

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This drops all the old drmSupports* checks since KMS does them all, and it
also drop R300_CLASS and R600_CLASS.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Dave Airlie
2011-10-29 08:39:54 +01:00
parent e252af3406
commit 56d30bb00d
15 changed files with 102 additions and 553 deletions
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32
src/mesa/drivers/dri/r200/r200_context.c
View File

@@ -294,10 +294,7 @@ GLboolean r200CreateContext( gl_api api,
ctx->Const.MinPointSizeAA = 1.0;
ctx->Const.MaxPointSizeAA = 1.0;
ctx->Const.PointSizeGranularity = 0.0625;
if (rmesa->radeon.radeonScreen->drmSupportsPointSprites)
ctx->Const.MaxPointSize = 2047.0;
else
ctx->Const.MaxPointSize = 1.0;
ctx->Const.MaxPointSize = 2047.0;
/* mesa initialization problem - _mesa_init_point was already called */
ctx->Point.MaxSize = ctx->Const.MaxPointSize;
@@ -359,8 +356,7 @@ GLboolean r200CreateContext( gl_api api,
ctx->Extensions.ARB_texture_env_dot3 = true;
ctx->Extensions.ARB_texture_env_crossbar = true;
ctx->Extensions.ARB_vertex_array_object = true;
ctx->Extensions.EXT_blend_color =
rmesa->radeon.radeonScreen->drmSupportsBlendColor;
ctx->Extensions.EXT_blend_color = true;
ctx->Extensions.EXT_blend_minmax = true;
ctx->Extensions.EXT_fog_coord = true;
ctx->Extensions.EXT_packed_depth_stencil = true;
@@ -394,29 +390,21 @@ GLboolean r200CreateContext( gl_api api,
ctx->Extensions.EXT_texture_compression_s3tc = true;
}
ctx->Extensions.ARB_texture_cube_map =
rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200;
ctx->Extensions.ARB_texture_cube_map = true;
if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
ctx->Extensions.EXT_blend_equation_separate = true;
ctx->Extensions.EXT_blend_func_separate = true;
}
ctx->Extensions.EXT_blend_equation_separate = true;
ctx->Extensions.EXT_blend_func_separate = true;
if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
ctx->Extensions.ARB_vertex_program = true;
ctx->Extensions.EXT_gpu_program_parameters = true;
}
ctx->Extensions.ARB_vertex_program = true;
ctx->Extensions.EXT_gpu_program_parameters = true;
ctx->Extensions.NV_vertex_program =
driQueryOptionb(&rmesa->radeon.optionCache, "nv_vertex_program");
ctx->Extensions.ATI_fragment_shader = (ctx->Const.MaxTextureUnits == 6)
&& rmesa->radeon.radeonScreen->drmSupportsFragShader;
ctx->Extensions.ATI_fragment_shader = (ctx->Const.MaxTextureUnits == 6);
if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
ctx->Extensions.ARB_point_sprite = true;
ctx->Extensions.EXT_point_parameters = true;
}
ctx->Extensions.ARB_point_sprite = true;
ctx->Extensions.EXT_point_parameters = true;
#if 0
r200InitDriverFuncs( ctx );

48
src/mesa/drivers/dri/r200/r200_state.c
View File

@@ -115,8 +115,7 @@ static void r200BlendColor( struct gl_context *ctx, const GLfloat cf[4] )
CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]);
CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]);
CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]);
if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = radeonPackColor( 4, color[0], color[1], color[2], color[3] );
rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = radeonPackColor( 4, color[0], color[1], color[2], color[3] );
}
/**
@@ -214,35 +213,19 @@ static void r200_set_blend_state( struct gl_context * ctx )
R200_STATECHANGE( rmesa, ctx );
if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
if (ctx->Color.ColorLogicOpEnabled) {
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE;
rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqn | func;
rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = eqn | func;
return;
} else if (ctx->Color.BlendEnabled) {
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE;
}
else {
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl;
rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqn | func;
rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = eqn | func;
return;
}
if (ctx->Color.ColorLogicOpEnabled) {
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE;
rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqn | func;
rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = eqn | func;
return;
} else if (ctx->Color.BlendEnabled) {
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE;
}
else {
if (ctx->Color.ColorLogicOpEnabled) {
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE;
rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = eqn | func;
return;
} else if (ctx->Color.BlendEnabled) {
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE;
}
else {
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl;
rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = eqn | func;
return;
}
rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl;
rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqn | func;
rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = eqn | func;
return;
}
func = (blend_factor( ctx->Color.Blend[0].SrcRGB, GL_TRUE ) << R200_SRC_BLEND_SHIFT) |
@@ -279,11 +262,6 @@ static void r200_set_blend_state( struct gl_context * ctx )
return;
}
if (!rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = eqn | func;
return;
}
funcA = (blend_factor( ctx->Color.Blend[0].SrcA, GL_TRUE ) << R200_SRC_BLEND_SHIFT) |
(blend_factor( ctx->Color.Blend[0].DstA, GL_FALSE ) << R200_DST_BLEND_SHIFT);
@@ -2144,8 +2122,6 @@ static void r200Enable( struct gl_context *ctx, GLenum cap, GLboolean state )
rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] &=
~(R200_TXFORMAT_ST_ROUTE_MASK | R200_TXFORMAT_LOOKUP_DISABLE);
rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] |= unit << R200_TXFORMAT_ST_ROUTE_SHIFT;
/* need to guard this with drmSupportsFragmentShader? Should never get here if
we don't announce ATI_fs, right? */
rmesa->hw.tex[unit].cmd[TEX_PP_TXMULTI_CTL] = 0;
}
R200_STATECHANGE( rmesa, cst );

177
src/mesa/drivers/dri/r200/r200_state_init.c
View File

@@ -654,10 +654,7 @@ void r200InitState( r200ContextPtr rmesa )
/* Allocate state buffers:
*/
if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
else
ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
rmesa->hw.ctx.emit = ctx_emit_cs;
rmesa->hw.ctx.check = check_always_ctx;
@@ -674,76 +671,47 @@ void r200InitState( r200ContextPtr rmesa )
ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 );
{
int state_size = TEX_STATE_SIZE_NEWDRM;
if (!rmesa->radeon.radeonScreen->drmSupportsFragShader) {
state_size = TEX_STATE_SIZE_OLDDRM;
if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
/* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
ALLOC_STATE( tex[0], tex_pair_mm, state_size, "TEX/tex-0", 0 );
ALLOC_STATE( tex[1], tex_pair_mm, state_size, "TEX/tex-1", 1 );
ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
}
if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) {
/* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
ALLOC_STATE( tex[0], tex_pair_mm, state_size, "TEX/tex-0", 0 );
ALLOC_STATE( tex[1], tex_pair_mm, state_size, "TEX/tex-1", 1 );
ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
}
else {
ALLOC_STATE( tex[0], tex_mm, state_size, "TEX/tex-0", 0 );
ALLOC_STATE( tex[1], tex_mm, state_size, "TEX/tex-1", 1 );
ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
}
ALLOC_STATE( tex[2], tex_mm, state_size, "TEX/tex-2", 2 );
ALLOC_STATE( tex[3], tex_mm, state_size, "TEX/tex-3", 3 );
ALLOC_STATE( tex[4], tex_mm, state_size, "TEX/tex-4", 4 );
ALLOC_STATE( tex[5], tex_mm, state_size, "TEX/tex-5", 5 );
if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
} else {
ALLOC_STATE( atf, never, ATF_STATE_SIZE, "ATF/tfactor", 0 );
ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
}
else {
ALLOC_STATE( tex[0], tex_mm, state_size, "TEX/tex-0", 0 );
ALLOC_STATE( tex[1], tex_mm, state_size, "TEX/tex-1", 1 );
ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
}
ALLOC_STATE( tex[2], tex_mm, state_size, "TEX/tex-2", 2 );
ALLOC_STATE( tex[3], tex_mm, state_size, "TEX/tex-3", 3 );
ALLOC_STATE( tex[4], tex_mm, state_size, "TEX/tex-4", 4 );
ALLOC_STATE( tex[5], tex_mm, state_size, "TEX/tex-5", 5 );
ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 );
ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 );
ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 );
}
ALLOC_STATE( stp, polygon_stipple, STP_STATE_SIZE, "STP/stp", 0 );
for (i = 0; i < 6; i++)
rmesa->hw.tex[i].emit = tex_emit_mm;
if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) {
ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
for (i = 0; i < 6; i++) {
rmesa->hw.cube[i].emit = cube_emit_cs;
rmesa->hw.cube[i].check = check_tex_cube_cs;
}
}
else {
ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
for (i = 0; i < 6; i++) {
rmesa->hw.cube[i].emit = cube_emit_cs;
rmesa->hw.cube[i].check = check_tex_cube_cs;
}
if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) {
ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
ALLOC_STATE( vpi[0], tcl_vp_add4, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
ALLOC_STATE( vpi[1], tcl_vp_size_add4, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
ALLOC_STATE( vpp[0], tcl_vp_add4, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
ALLOC_STATE( vpp[1], tcl_vpp_size_add4, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
}
else {
ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
}
ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 );
ALLOC_STATE( vpi[0], tcl_vp_add4, VPI_STATE_SIZE, "VP/vertexprog-0", 0 );
ALLOC_STATE( vpi[1], tcl_vp_size_add4, VPI_STATE_SIZE, "VP/vertexprog-1", 1 );
ALLOC_STATE( vpp[0], tcl_vp_add4, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 );
ALLOC_STATE( vpp[1], tcl_vpp_size_add4, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 );
/* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */
ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 );
ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
@@ -784,20 +752,9 @@ void r200InitState( r200ContextPtr rmesa )
ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) {
ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
}
else {
ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
}
if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) {
ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
ALLOC_STATE( ptp, tcl_add8, PTP_STATE_SIZE, "PTP/pointparams", 0 );
}
else {
ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 );
}
ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 );
ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 );
ALLOC_STATE( ptp, tcl_add8, PTP_STATE_SIZE, "PTP/pointparams", 0 );
r200SetUpAtomList( rmesa );
@@ -806,8 +763,7 @@ void r200InitState( r200ContextPtr rmesa )
rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
if (rmesa->radeon.radeonScreen->drmSupportsBlendColor)
rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR);
rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
@@ -823,34 +779,19 @@ void r200InitState( r200ContextPtr rmesa )
rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3);
rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0);
if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
} else {
rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0);
rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1);
rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2);
rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3);
rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4);
rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5);
rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
}
rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR);
rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0);
rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0);
rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1);
rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1);
rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2);
rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2);
rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3);
rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3);
rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4);
rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4);
rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5);
rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5);
rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0);
rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1);
rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL);
@@ -994,15 +935,13 @@ void r200InitState( r200ContextPtr rmesa )
(R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
(R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
(R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
(R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
(R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
(R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
}
rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
@@ -1146,16 +1085,10 @@ void r200InitState( r200ContextPtr rmesa )
rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
(/* R200_TEXCOORD_PROJ | */
R200_LOD_BIAS_CORRECTION); /* Small default bias */
if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] =
rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
}
else {
rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] =
rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
}
rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0;
rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0;
rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =

3
src/mesa/drivers/dri/r200/r200_swtcl.c
View File

@@ -319,8 +319,7 @@ static INLINE GLuint reduced_hw_prim( struct gl_context *ctx, GLuint prim)
{
switch (prim) {
case GL_POINTS:
return (((R200_CONTEXT(ctx))->radeon.radeonScreen->drmSupportsPointSprites &&
!(ctx->_TriangleCaps & DD_POINT_SMOOTH)) ?
return ((!(ctx->_TriangleCaps & DD_POINT_SMOOTH)) ?
R200_VF_PRIM_POINT_SPRITES : R200_VF_PRIM_POINTS);
case GL_LINES:
/* fallthrough */

3
src/mesa/drivers/dri/r200/r200_tcl.c
View File

@@ -68,8 +68,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define HAVE_ELTS 1
#define HW_POINTS (((R200_CONTEXT(ctx))->radeon.radeonScreen->drmSupportsPointSprites && \
!(ctx->_TriangleCaps & DD_POINT_SMOOTH)) ? \
#define HW_POINTS ((!(ctx->_TriangleCaps & DD_POINT_SMOOTH)) ? \
R200_VF_PRIM_POINT_SPRITES : R200_VF_PRIM_POINTS)
#define HW_LINES R200_VF_PRIM_LINES
#define HW_LINE_LOOP 0

8
src/mesa/drivers/dri/r200/r200_texstate.c
View File

@@ -1090,11 +1090,9 @@ static void import_tex_obj_state( r200ContextPtr rmesa,
R200_STATECHANGE( rmesa, cube[unit] );
cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces;
if (rmesa->radeon.radeonScreen->drmSupportsFragShader) {
/* that value is submitted twice. could change cube atom
to not include that command when new drm is used */
cmd[TEX_PP_CUBIC_FACES] = texobj->pp_cubic_faces;
}
/* that value is submitted twice. could change cube atom
to not include that command when new drm is used */
cmd[TEX_PP_CUBIC_FACES] = texobj->pp_cubic_faces;
}
}

3
src/mesa/drivers/dri/r200/r200_vertprog.c
View File

@@ -1109,8 +1109,7 @@ void r200SetupVertexProg( struct gl_context *ctx ) {
r200_translate_vertex_program(ctx, vp);
}
/* could optimize setting up vertex progs away for non-tcl hw */
fallback = !(vp->native && r200VertexProgUpdateParams(ctx, vp) &&
rmesa->radeon.radeonScreen->drmSupportsVertexProgram);
fallback = !(vp->native && r200VertexProgUpdateParams(ctx, vp));
TCL_FALLBACK(ctx, R200_TCL_FALLBACK_VERTEX_PROGRAM, fallback);
if (rmesa->radeon.TclFallback) return;

4
src/mesa/drivers/dri/radeon/radeon_cmdbuf.h
View File

@@ -100,10 +100,6 @@ void rcommonBeginBatch(radeonContextPtr rmesa,
#define OUT_BATCH_REGSEQ(reg, count) \
OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
/** Write a 32 bit float to the ring; requires 1 dword. */
#define OUT_BATCH_FLOAT32(f) \
OUT_BATCH(radeonPackFloat32((f)))
/* +r6/r7 : code here moved */
/* Fire the buffered vertices no matter what.

55
src/mesa/drivers/dri/radeon/radeon_common_context.c
View File

@@ -117,12 +117,7 @@ static const GLubyte *radeonGetString(struct gl_context * ctx, GLenum name)
switch (name) {
case GL_VENDOR:
if (IS_R600_CLASS(radeon->radeonScreen))
return (GLubyte *) "Advanced Micro Devices, Inc.";
else if (IS_R300_CLASS(radeon->radeonScreen))
return (GLubyte *) "DRI R300 Project";
else
return (GLubyte *) "Tungsten Graphics, Inc.";
return (GLubyte *) "Tungsten Graphics, Inc.";
case GL_RENDERER:
{
@@ -132,11 +127,7 @@ static const GLubyte *radeonGetString(struct gl_context * ctx, GLenum name)
const char* chipclass;
char hardwarename[32];
if (IS_R600_CLASS(radeon->radeonScreen))
chipclass = "R600";
else if (IS_R300_CLASS(radeon->radeonScreen))
chipclass = "R300";
else if (IS_R200_CLASS(radeon->radeonScreen))
if (IS_R200_CLASS(radeon->radeonScreen))
chipclass = "R200";
else
chipclass = "R100";
@@ -148,20 +139,11 @@ static const GLubyte *radeonGetString(struct gl_context * ctx, GLenum name)
offset = driGetRendererString(buffer, hardwarename, agp_mode);
if (IS_R600_CLASS(radeon->radeonScreen)) {
sprintf(&buffer[offset], " TCL");
} else if (IS_R300_CLASS(radeon->radeonScreen)) {
sprintf(&buffer[offset], " %sTCL",
(radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)
? "" : "NO-");
} else {
sprintf(&buffer[offset], " %sTCL",
!(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
? "" : "NO-");
}
sprintf(&buffer[offset], " %sTCL",
!(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
? "" : "NO-");
if (radeon->radeonScreen->driScreen->dri2.enabled)
strcat(buffer, " DRI2");
strcat(buffer, " DRI2");
return (GLubyte *) buffer;
}
@@ -246,25 +228,11 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
radeon->texture_depth = ( glVisual->rgbBits > 16 ) ?
DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
if (IS_R600_CLASS(radeon->radeonScreen)) {
radeon->texture_row_align = radeon->radeonScreen->group_bytes;
radeon->texture_rect_row_align = radeon->radeonScreen->group_bytes;
radeon->texture_compressed_row_align = radeon->radeonScreen->group_bytes;
} else if (IS_R200_CLASS(radeon->radeonScreen) ||
IS_R100_CLASS(radeon->radeonScreen)) {
if (IS_R200_CLASS(radeon->radeonScreen) ||
IS_R100_CLASS(radeon->radeonScreen)) {
radeon->texture_row_align = 32;
radeon->texture_rect_row_align = 64;
radeon->texture_compressed_row_align = 32;
} else { /* R300 - not sure this is all correct */
int chip_family = radeon->radeonScreen->chip_family;
if (chip_family == CHIP_FAMILY_RS600 ||
chip_family == CHIP_FAMILY_RS690 ||
chip_family == CHIP_FAMILY_RS740)
radeon->texture_row_align = 64;
else
radeon->texture_row_align = 32;
radeon->texture_rect_row_align = 64;
radeon->texture_compressed_row_align = 32;
}
radeon_init_dma(radeon);
@@ -640,13 +608,6 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable,
rb->base.Height = drawable->h;
rb->has_surface = 0;
/* r6xx+ tiling */
rb->tile_config = radeon->radeonScreen->tile_config;
rb->group_bytes = radeon->radeonScreen->group_bytes;
rb->num_channels = radeon->radeonScreen->num_channels;
rb->num_banks = radeon->radeonScreen->num_banks;
rb->r7xx_bank_op = radeon->radeonScreen->r7xx_bank_op;
if (buffers[i].attachment == __DRI_BUFFER_STENCIL && depth_bo) {
if (RADEON_DEBUG & RADEON_DRI)
fprintf(stderr, "(reusing depth buffer as stencil)\n");

74
src/mesa/drivers/dri/radeon/radeon_common_context.h
View File

@@ -93,13 +93,6 @@ struct radeon_renderbuffer
GLuint pf_pending; /**< sequence number of pending flip */
__DRIdrawable *dPriv;
/* r6xx+ tiling */
GLuint tile_config;
GLint group_bytes;
GLint num_channels;
GLint num_banks;
GLint r7xx_bank_op;
};
struct radeon_framebuffer
@@ -225,29 +218,7 @@ struct radeon_tex_obj {
GLuint pp_txfilter_1; /* r300 */
/* r700 texture states */
GLuint SQ_TEX_RESOURCE0;
GLuint SQ_TEX_RESOURCE1;
GLuint SQ_TEX_RESOURCE2;
GLuint SQ_TEX_RESOURCE3;
GLuint SQ_TEX_RESOURCE4;
GLuint SQ_TEX_RESOURCE5;
GLuint SQ_TEX_RESOURCE6;
GLuint SQ_TEX_RESOURCE7;
GLuint SQ_TEX_SAMPLER0;
GLuint SQ_TEX_SAMPLER1;
GLuint SQ_TEX_SAMPLER2;
GLuint TD_PS_SAMPLER0_BORDER_RED;
GLuint TD_PS_SAMPLER0_BORDER_GREEN;
GLuint TD_PS_SAMPLER0_BORDER_BLUE;
GLuint TD_PS_SAMPLER0_BORDER_ALPHA;
GLboolean border_fallback;
};
static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
@@ -550,51 +521,6 @@ static inline __DRIdrawable* radeon_get_readable(radeonContextPtr radeon)
return radeon->dri.context->driReadablePriv;
}
/**
* This function takes a float and packs it into a uint32_t
*/
static INLINE uint32_t radeonPackFloat32(float fl)
{
union {
float fl;
uint32_t u;
} u;
u.fl = fl;
return u.u;
}
/* This is probably wrong for some values, I need to test this
* some more. Range checking would be a good idea also..
*
* But it works for most things. I'll fix it later if someone
* else with a better clue doesn't
*/
static INLINE uint32_t radeonPackFloat24(float f)
{
float mantissa;
int exponent;
uint32_t float24 = 0;
if (f == 0.0)
return 0;
mantissa = frexpf(f, &exponent);
/* Handle -ve */
if (mantissa < 0) {
float24 |= (1 << 23);
mantissa = mantissa * -1.0;
}
/* Handle exponent, bias of 63 */
exponent += 62;
float24 |= (exponent << 16);
/* Kill 7 LSB of mantissa */
float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;
return float24;
}
GLboolean radeonInitContext(radeonContextPtr radeon,
struct dd_function_table* functions,
const struct gl_config * glVisual,

3
src/mesa/drivers/dri/radeon/radeon_context.c
View File

@@ -330,8 +330,7 @@ r100CreateContext( gl_api api,
ctx->Extensions.EXT_framebuffer_object = true;
ctx->Extensions.ARB_texture_cube_map =
rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100;
ctx->Extensions.ARB_texture_cube_map = true;
if (rmesa->radeon.glCtx->Mesa_DXTn) {
ctx->Extensions.EXT_texture_compression_s3tc = true;

36
src/mesa/drivers/dri/radeon/radeon_queryobj.c
View File

@@ -35,10 +35,9 @@
static void radeonQueryGetResult(struct gl_context *ctx, struct gl_query_object *q)
{
radeonContextPtr radeon = RADEON_CONTEXT(ctx);
struct radeon_query_object *query = (struct radeon_query_object *)q;
uint32_t *result;
int i, max_idx;
int i;
radeon_print(RADEON_STATE, RADEON_VERBOSE,
"%s: query id %d, result %d\n",
@@ -48,36 +47,9 @@ static void radeonQueryGetResult(struct gl_context *ctx, struct gl_query_object
result = query->bo->ptr;
query->Base.Result = 0;
if (IS_R600_CLASS(radeon->radeonScreen)) {
/* ZPASS EVENT writes alternating qwords
* At query start we set the start offset to 0 and
* hw writes zpass start counts to qwords 0, 2, 4, 6.
* At query end we set the start offset to 8 and
* hw writes zpass end counts to qwords 1, 3, 5, 7.
* then we substract. MSB is the valid bit.
*/
if (radeon->radeonScreen->chip_family >= CHIP_FAMILY_CEDAR)
max_idx = 8 * 4; /* 8 DB's */
else
max_idx = 4 * 4; /* 4 DB's for r600, r700 */
for (i = 0; i < max_idx; i += 4) {
uint64_t start = (uint64_t)LE32_TO_CPU(result[i]) |
(uint64_t)LE32_TO_CPU(result[i + 1]) << 32;
uint64_t end = (uint64_t)LE32_TO_CPU(result[i + 2]) |
(uint64_t)LE32_TO_CPU(result[i + 3]) << 32;
if ((start & 0x8000000000000000) && (end & 0x8000000000000000)) {
uint64_t query_count = end - start;
query->Base.Result += query_count;
}
radeon_print(RADEON_STATE, RADEON_TRACE,
"%d start: %" PRIu64 ", end: %" PRIu64 " %" PRIu64 "\n", i, start, end, end - start);
}
} else {
for (i = 0; i < query->curr_offset/sizeof(uint32_t); ++i) {
query->Base.Result += LE32_TO_CPU(result[i]);
radeon_print(RADEON_STATE, RADEON_TRACE, "result[%d] = %d\n", i, LE32_TO_CPU(result[i]));
}
for (i = 0; i < query->curr_offset/sizeof(uint32_t); ++i) {
query->Base.Result += LE32_TO_CPU(result[i]);
radeon_print(RADEON_STATE, RADEON_TRACE, "result[%d] = %d\n", i, LE32_TO_CPU(result[i]));
}
radeon_bo_unmap(query->bo);

170
src/mesa/drivers/dri/radeon/radeon_screen.c
View File

@@ -1057,7 +1057,6 @@ radeonCreateScreen2(__DRIscreen *sPriv)
int i;
int ret;
uint32_t device_id = 0;
uint32_t temp = 0;
/* Allocate the private area */
screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
@@ -1076,15 +1075,6 @@ radeonCreateScreen2(__DRIscreen *sPriv)
screen->chip_flags = 0;
/* if we have kms we can support all of these */
screen->drmSupportsCubeMapsR200 = 1;
screen->drmSupportsBlendColor = 1;
screen->drmSupportsTriPerf = 1;
screen->drmSupportsFragShader = 1;
screen->drmSupportsPointSprites = 1;
screen->drmSupportsCubeMapsR100 = 1;
screen->drmSupportsVertexProgram = 1;
screen->drmSupportsOcclusionQueries = 1;
screen->irq = 1;
ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
@@ -1105,166 +1095,6 @@ radeonCreateScreen2(__DRIscreen *sPriv)
screen->chip_flags |= RADEON_CLASS_R100;
else if (screen->chip_family <= CHIP_FAMILY_RV280)
screen->chip_flags |= RADEON_CLASS_R200;
else if (screen->chip_family <= CHIP_FAMILY_RV570)
screen->chip_flags |= RADEON_CLASS_R300;
else
screen->chip_flags |= RADEON_CLASS_R600;
/* r6xx+ tiling, default group bytes */
if (screen->chip_family >= CHIP_FAMILY_CEDAR)
screen->group_bytes = 512;
else
screen->group_bytes = 256;
if (IS_R600_CLASS(screen)) {
if ((sPriv->drm_version.minor >= 6) &&
(screen->chip_family < CHIP_FAMILY_CEDAR)) {
ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
if (ret)
fprintf(stderr, "failed to get tiling info\n");
else {
screen->tile_config = temp;
screen->r7xx_bank_op = 0;
switch ((screen->tile_config & 0xe) >> 1) {
case 0:
screen->num_channels = 1;
break;
case 1:
screen->num_channels = 2;
break;
case 2:
screen->num_channels = 4;
break;
case 3:
screen->num_channels = 8;
break;
default:
fprintf(stderr, "bad channels\n");
break;
}
switch ((screen->tile_config & 0x30) >> 4) {
case 0:
screen->num_banks = 4;
break;
case 1:
screen->num_banks = 8;
break;
default:
fprintf(stderr, "bad banks\n");
break;
}
switch ((screen->tile_config & 0xc0) >> 6) {
case 0:
screen->group_bytes = 256;
break;
case 1:
screen->group_bytes = 512;
break;
default:
fprintf(stderr, "bad group_bytes\n");
break;
}
}
} else if ((sPriv->drm_version.minor >= 7) &&
(screen->chip_family >= CHIP_FAMILY_CEDAR)) {
ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
if (ret)
fprintf(stderr, "failed to get tiling info\n");
else {
screen->tile_config = temp;
screen->r7xx_bank_op = 0;
switch (screen->tile_config & 0xf) {
case 0:
screen->num_channels = 1;
break;
case 1:
screen->num_channels = 2;
break;
case 2:
screen->num_channels = 4;
break;
case 3:
screen->num_channels = 8;
break;
default:
fprintf(stderr, "bad channels\n");
break;
}
switch ((screen->tile_config & 0xf0) >> 4) {
case 0:
screen->num_banks = 4;
break;
case 1:
screen->num_banks = 8;
break;
case 2:
screen->num_banks = 16;
break;
default:
fprintf(stderr, "bad banks\n");
break;
}
switch ((screen->tile_config & 0xf00) >> 8) {
case 0:
screen->group_bytes = 256;
break;
case 1:
screen->group_bytes = 512;
break;
default:
fprintf(stderr, "bad group_bytes\n");
break;
}
}
}
}
if (IS_R300_CLASS(screen)) {
ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
if (ret) {
fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
switch (screen->chip_family) {
case CHIP_FAMILY_R300:
case CHIP_FAMILY_R350:
screen->num_gb_pipes = 2;
break;
case CHIP_FAMILY_R420:
case CHIP_FAMILY_R520:
case CHIP_FAMILY_R580:
case CHIP_FAMILY_RV560:
case CHIP_FAMILY_RV570:
screen->num_gb_pipes = 4;
break;
case CHIP_FAMILY_RV350:
case CHIP_FAMILY_RV515:
case CHIP_FAMILY_RV530:
case CHIP_FAMILY_RV410:
default:
screen->num_gb_pipes = 1;
break;
}
} else {
screen->num_gb_pipes = temp;
}
/* pipe overrides */
switch (device_id) {
case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
screen->num_gb_pipes = 1;
break;
default:
break;
}
ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
if (ret)
screen->num_z_pipes = 2;
else
screen->num_z_pipes = temp;
}
i = 0;
screen->extensions[i++] = &driCopySubBufferExtension.base;

18
src/mesa/drivers/dri/radeon/radeon_screen.h
View File

@@ -92,14 +92,6 @@ typedef struct radeon_screen {
unsigned int gart_texture_offset; /* offset in card memory space */
unsigned int gart_base;
GLboolean drmSupportsCubeMapsR200; /* need radeon kernel module >= 1.7 */
GLboolean drmSupportsBlendColor; /* need radeon kernel module >= 1.11 */
GLboolean drmSupportsTriPerf; /* need radeon kernel module >= 1.16 */
GLboolean drmSupportsFragShader; /* need radeon kernel module >= 1.18 */
GLboolean drmSupportsPointSprites; /* need radeon kernel module >= 1.13 */
GLboolean drmSupportsCubeMapsR100; /* need radeon kernel module >= 1.15 */
GLboolean drmSupportsVertexProgram; /* need radeon kernel module >= 1.25 */
GLboolean drmSupportsOcclusionQueries; /* need radeon kernel module >= 1.30 */
GLboolean depthHasSurface;
/* Configuration cache with default values for all contexts */
@@ -112,12 +104,6 @@ typedef struct radeon_screen {
drm_radeon_sarea_t *sarea; /* Private SAREA data */
struct radeon_bo_manager *bom;
/* r6xx+ tiling */
GLuint tile_config;
GLint group_bytes;
GLint num_channels;
GLint num_banks;
GLint r7xx_bank_op;
} radeonScreenRec, *radeonScreenPtr;
struct __DRIimageRec {
@@ -135,10 +121,6 @@ struct __DRIimageRec {
((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R100)
#define IS_R200_CLASS(screen) \
((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R200)
#define IS_R300_CLASS(screen) \
((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R300)
#define IS_R600_CLASS(screen) \
((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R600)
extern void radeonDestroyBuffer(__DRIdrawable *driDrawPriv);
#endif /* __RADEON_SCREEN_H__ */

21
src/mesa/drivers/dri/radeon/radeon_state_init.c
View File

@@ -202,7 +202,6 @@ static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom )
CHECK( always, GL_TRUE, 0 )
CHECK( always_add2, GL_TRUE, 2 )
CHECK( always_add4, GL_TRUE, 4 )
CHECK( never, GL_FALSE, 0 )
CHECK( tex0_mm, ctx->Texture.Unit[0]._ReallyEnabled, 3 )
CHECK( tex1_mm, ctx->Texture.Unit[1]._ReallyEnabled, 3 )
/* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */
@@ -586,20 +585,12 @@ void radeonInitState( r100ContextPtr rmesa )
for (i = 0; i < 3; i++) {
rmesa->hw.tex[i].emit = tex_emit_cs;
}
if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
{
ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
for (i = 0; i < 3; i++)
rmesa->hw.cube[i].emit = cube_emit_cs;
}
else
{
ALLOC_STATE_IDX( cube[0], never, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
ALLOC_STATE_IDX( cube[1], never, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
ALLOC_STATE_IDX( cube[2], never, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
}
ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
for (i = 0; i < 3; i++)
rmesa->hw.cube[i].emit = cube_emit_cs;
ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 );
ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 );
ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 );