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ilo: use an accessor for dev->gen

Browse Source 
It should enable us to do specialized builds by making the accessor return a
constant.
This commit is contained in:
Chia-I Wu
2014-09-12 10:55:58 +08:00
parent ea5de3e0bd
commit 56d2ebb019
24 changed files with 198 additions and 171 deletions
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6
src/gallium/drivers/ilo/ilo_3d.c
View File

@@ -627,7 +627,7 @@ ilo_check_restart_index(const struct ilo_context *ilo, unsigned restart_index)
* Haswell (GEN(7.5)) supports an arbitrary cut index, check everything
* older.
*/
if (ilo->dev->gen >= ILO_GEN(7.5))
if (ilo_dev_gen(ilo->dev) >= ILO_GEN(7.5))
return true;
/* Note: indices must be unsigned byte, unsigned short or unsigned int */
@@ -663,7 +663,7 @@ ilo_check_restart_prim_type(const struct ilo_context *ilo, unsigned prim)
case PIPE_PRIM_QUAD_STRIP:
case PIPE_PRIM_QUADS:
case PIPE_PRIM_TRIANGLE_FAN:
if (ilo->dev->gen >= ILO_GEN(7.5)) {
if (ilo_dev_gen(ilo->dev) >= ILO_GEN(7.5)) {
/* Haswell and newer parts can handle these prim types. */
return true;
}
@@ -816,7 +816,7 @@ ilo_texture_barrier(struct pipe_context *pipe)
ilo_3d_pipeline_emit_flush(hw3d->pipeline);
/* don't know why */
if (ilo->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(ilo->dev) >= ILO_GEN(7))
ilo_cp_flush(hw3d->cp, "texture barrier");
}

6
src/gallium/drivers/ilo/ilo_3d_pipeline.c
View File

@@ -77,7 +77,7 @@ ilo_3d_pipeline_create(struct ilo_cp *cp, const struct ilo_dev_info *dev)
p->cp = cp;
p->dev = dev;
switch (p->dev->gen) {
switch (ilo_dev_gen(p->dev)) {
case ILO_GEN(6):
ilo_3d_pipeline_init_gen6(p);
break;
@@ -137,7 +137,7 @@ static void
handle_invalid_batch_bo(struct ilo_3d_pipeline *p, bool unset)
{
if (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_BATCH_BO) {
if (p->dev->gen == ILO_GEN(6))
if (ilo_dev_gen(p->dev) == ILO_GEN(6))
p->state.has_gen6_wa_pipe_control = false;
if (unset)
@@ -166,7 +166,7 @@ ilo_3d_pipeline_emit_draw(struct ilo_3d_pipeline *p,
p->state.so_num_vertices = 0;
/* on GEN7+, we need SOL_RESET to reset the SO write offsets */
if (p->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(p->dev) >= ILO_GEN(7))
ilo_cp_set_one_off_flags(p->cp, INTEL_EXEC_GEN7_SOL_RESET);
}

58
src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c
View File

@@ -50,7 +50,7 @@ static void
gen6_wa_pipe_control_post_sync(struct ilo_3d_pipeline *p,
bool caller_post_sync)
{
assert(p->dev->gen == ILO_GEN(6));
assert(ilo_dev_gen(p->dev) == ILO_GEN(6));
/* emit once */
if (p->state.has_gen6_wa_pipe_control)
@@ -93,7 +93,7 @@ gen6_wa_pipe_control_post_sync(struct ilo_3d_pipeline *p,
static void
gen6_wa_pipe_control_wm_multisample_flush(struct ilo_3d_pipeline *p)
{
assert(p->dev->gen == ILO_GEN(6));
assert(ilo_dev_gen(p->dev) == ILO_GEN(6));
gen6_wa_pipe_control_post_sync(p, false);
@@ -114,7 +114,7 @@ gen6_wa_pipe_control_wm_multisample_flush(struct ilo_3d_pipeline *p)
static void
gen6_wa_pipe_control_wm_depth_flush(struct ilo_3d_pipeline *p)
{
assert(p->dev->gen == ILO_GEN(6));
assert(ilo_dev_gen(p->dev) == ILO_GEN(6));
gen6_wa_pipe_control_post_sync(p, false);
@@ -139,7 +139,7 @@ gen6_wa_pipe_control_wm_depth_flush(struct ilo_3d_pipeline *p)
static void
gen6_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
{
assert(p->dev->gen == ILO_GEN(6));
assert(ilo_dev_gen(p->dev) == ILO_GEN(6));
/* the post-sync workaround should cover this already */
if (p->state.has_gen6_wa_pipe_control)
@@ -161,7 +161,7 @@ gen6_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
static void
gen6_wa_pipe_control_vs_const_flush(struct ilo_3d_pipeline *p)
{
assert(p->dev->gen == ILO_GEN(6));
assert(ilo_dev_gen(p->dev) == ILO_GEN(6));
gen6_wa_pipe_control_post_sync(p, false);
@@ -186,7 +186,7 @@ gen6_pipeline_common_select(struct ilo_3d_pipeline *p,
{
/* PIPELINE_SELECT */
if (session->hw_ctx_changed) {
if (p->dev->gen == ILO_GEN(6))
if (ilo_dev_gen(p->dev) == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
gen6_PIPELINE_SELECT(&p->cp->builder, 0x0);
@@ -200,7 +200,7 @@ gen6_pipeline_common_sip(struct ilo_3d_pipeline *p,
{
/* STATE_SIP */
if (session->hw_ctx_changed) {
if (p->dev->gen == ILO_GEN(6))
if (ilo_dev_gen(p->dev) == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
gen6_STATE_SIP(&p->cp->builder, 0);
@@ -215,7 +215,7 @@ gen6_pipeline_common_base_address(struct ilo_3d_pipeline *p,
/* STATE_BASE_ADDRESS */
if (session->state_bo_changed || session->kernel_bo_changed ||
session->batch_bo_changed) {
if (p->dev->gen == ILO_GEN(6))
if (ilo_dev_gen(p->dev) == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
ilo_builder_batch_state_base_address(&p->cp->builder,
@@ -399,7 +399,7 @@ gen6_pipeline_vf(struct ilo_3d_pipeline *p,
const struct ilo_context *ilo,
struct gen6_pipeline_session *session)
{
if (p->dev->gen >= ILO_GEN(7.5)) {
if (ilo_dev_gen(p->dev) >= ILO_GEN(7.5)) {
/* 3DSTATE_INDEX_BUFFER */
if (DIRTY(IB) || session->batch_bo_changed) {
gen6_3DSTATE_INDEX_BUFFER(&p->cp->builder,
@@ -486,7 +486,7 @@ gen6_pipeline_vs(struct ilo_3d_pipeline *p,
* the classic i965 does this in upload_vs_state(), citing a spec that I
* cannot find
*/
if (emit_3dstate_vs && p->dev->gen == ILO_GEN(6))
if (emit_3dstate_vs && ilo_dev_gen(p->dev) == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
/* 3DSTATE_CONSTANT_VS */
@@ -504,7 +504,7 @@ gen6_pipeline_vs(struct ilo_3d_pipeline *p,
gen6_3DSTATE_VS(&p->cp->builder, ilo->vs, num_samplers);
}
if (emit_3dstate_constant_vs && p->dev->gen == ILO_GEN(6))
if (emit_3dstate_constant_vs && ilo_dev_gen(p->dev) == ILO_GEN(6))
gen6_wa_pipe_control_vs_const_flush(p);
}
@@ -579,7 +579,7 @@ gen6_pipeline_gs_svbi(struct ilo_3d_pipeline *p,
/* 3DSTATE_GS_SVB_INDEX */
if (emit) {
if (p->dev->gen == ILO_GEN(6))
if (ilo_dev_gen(p->dev) == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
gen6_3DSTATE_GS_SVB_INDEX(&p->cp->builder,
@@ -652,7 +652,7 @@ gen6_pipeline_sf_rect(struct ilo_3d_pipeline *p,
{
/* 3DSTATE_DRAWING_RECTANGLE */
if (DIRTY(FB)) {
if (p->dev->gen == ILO_GEN(6))
if (ilo_dev_gen(p->dev) == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
gen6_3DSTATE_DRAWING_RECTANGLE(&p->cp->builder, 0, 0,
@@ -681,7 +681,7 @@ gen6_pipeline_wm(struct ilo_3d_pipeline *p,
const bool cc_may_kill = (ilo->dsa->dw_alpha ||
ilo->blend->alpha_to_coverage);
if (p->dev->gen == ILO_GEN(6) && session->hw_ctx_changed)
if (ilo_dev_gen(p->dev) == ILO_GEN(6) && session->hw_ctx_changed)
gen6_wa_pipe_control_wm_max_threads_stall(p);
gen6_3DSTATE_WM(&p->cp->builder, ilo->fs, num_samplers,
@@ -701,7 +701,7 @@ gen6_pipeline_wm_multisample(struct ilo_3d_pipeline *p,
packed_sample_pos = (ilo->fb.num_samples > 1) ?
&p->packed_sample_position_4x : &p->packed_sample_position_1x;
if (p->dev->gen == ILO_GEN(6)) {
if (ilo_dev_gen(p->dev) == ILO_GEN(6)) {
gen6_wa_pipe_control_post_sync(p, false);
gen6_wa_pipe_control_wm_multisample_flush(p);
}
@@ -742,7 +742,7 @@ gen6_pipeline_wm_depth(struct ilo_3d_pipeline *p,
clear_params = 0;
}
if (p->dev->gen == ILO_GEN(6)) {
if (ilo_dev_gen(p->dev) == ILO_GEN(6)) {
gen6_wa_pipe_control_post_sync(p, false);
gen6_wa_pipe_control_wm_depth_flush(p);
}
@@ -762,7 +762,7 @@ gen6_pipeline_wm_raster(struct ilo_3d_pipeline *p,
/* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
if ((DIRTY(RASTERIZER) || DIRTY(POLY_STIPPLE)) &&
ilo->rasterizer->state.poly_stipple_enable) {
if (p->dev->gen == ILO_GEN(6))
if (ilo_dev_gen(p->dev) == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
gen6_3DSTATE_POLY_STIPPLE_PATTERN(&p->cp->builder,
@@ -773,7 +773,7 @@ gen6_pipeline_wm_raster(struct ilo_3d_pipeline *p,
/* 3DSTATE_LINE_STIPPLE */
if (DIRTY(RASTERIZER) && ilo->rasterizer->state.line_stipple_enable) {
if (p->dev->gen == ILO_GEN(6))
if (ilo_dev_gen(p->dev) == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
gen6_3DSTATE_LINE_STIPPLE(&p->cp->builder,
@@ -783,7 +783,7 @@ gen6_pipeline_wm_raster(struct ilo_3d_pipeline *p,
/* 3DSTATE_AA_LINE_PARAMETERS */
if (DIRTY(RASTERIZER) && ilo->rasterizer->state.line_smooth) {
if (p->dev->gen == ILO_GEN(6))
if (ilo_dev_gen(p->dev) == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
gen6_3DSTATE_AA_LINE_PARAMETERS(&p->cp->builder);
@@ -796,7 +796,7 @@ gen6_pipeline_state_viewports(struct ilo_3d_pipeline *p,
struct gen6_pipeline_session *session)
{
/* SF_CLIP_VIEWPORT and CC_VIEWPORT */
if (p->dev->gen >= ILO_GEN(7) && DIRTY(VIEWPORT)) {
if (ilo_dev_gen(p->dev) >= ILO_GEN(7) && DIRTY(VIEWPORT)) {
p->state.SF_CLIP_VIEWPORT = gen7_SF_CLIP_VIEWPORT(&p->cp->builder,
ilo->viewport.cso, ilo->viewport.count);
@@ -920,7 +920,7 @@ gen6_pipeline_state_surfaces_so(struct ilo_3d_pipeline *p,
{
const struct ilo_so_state *so = &ilo->so;
if (p->dev->gen != ILO_GEN(6))
if (ilo_dev_gen(p->dev) != ILO_GEN(6))
return;
/* SURFACE_STATEs for stream output targets */
@@ -1451,7 +1451,7 @@ ilo_3d_pipeline_emit_draw_gen6(struct ilo_3d_pipeline *p,
void
ilo_3d_pipeline_emit_flush_gen6(struct ilo_3d_pipeline *p)
{
if (p->dev->gen == ILO_GEN(6))
if (ilo_dev_gen(p->dev) == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
gen6_PIPE_CONTROL(&p->cp->builder,
@@ -1469,7 +1469,7 @@ void
ilo_3d_pipeline_emit_write_timestamp_gen6(struct ilo_3d_pipeline *p,
struct intel_bo *bo, int index)
{
if (p->dev->gen == ILO_GEN(6))
if (ilo_dev_gen(p->dev) == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, true);
gen6_PIPE_CONTROL(&p->cp->builder,
@@ -1482,7 +1482,7 @@ void
ilo_3d_pipeline_emit_write_depth_count_gen6(struct ilo_3d_pipeline *p,
struct intel_bo *bo, int index)
{
if (p->dev->gen == ILO_GEN(6))
if (ilo_dev_gen(p->dev) == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
gen6_PIPE_CONTROL(&p->cp->builder,
@@ -1505,8 +1505,8 @@ ilo_3d_pipeline_emit_write_statistics_gen6(struct ilo_3d_pipeline *p,
GEN6_REG_CL_INVOCATION_COUNT,
GEN6_REG_CL_PRIMITIVES_COUNT,
GEN6_REG_PS_INVOCATION_COUNT,
p->dev->gen >= ILO_GEN(7) ? GEN7_REG_HS_INVOCATION_COUNT : 0,
p->dev->gen >= ILO_GEN(7) ? GEN7_REG_DS_INVOCATION_COUNT : 0,
ilo_dev_gen(p->dev) >= ILO_GEN(7) ? GEN7_REG_HS_INVOCATION_COUNT : 0,
ilo_dev_gen(p->dev) >= ILO_GEN(7) ? GEN7_REG_DS_INVOCATION_COUNT : 0,
0,
};
int i;
@@ -1766,7 +1766,7 @@ gen6_pipeline_estimate_state_size(const struct ilo_3d_pipeline *p,
size += align(GEN6_COLOR_CALC_STATE__SIZE, alignment);
/* viewport arrays */
if (p->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(p->dev) >= ILO_GEN(7)) {
size +=
align(GEN7_SF_CLIP_VIEWPORT__SIZE * ILO_MAX_VIEWPORTS, 16) +
align(GEN6_CC_VIEWPORT__SIZE * ILO_MAX_VIEWPORTS, 8) +
@@ -1801,7 +1801,7 @@ gen6_pipeline_estimate_state_size(const struct ilo_3d_pipeline *p,
switch (sh_type) {
case PIPE_SHADER_VERTEX:
if (ilo->vs) {
if (p->dev->gen == ILO_GEN(6)) {
if (ilo_dev_gen(p->dev) == ILO_GEN(6)) {
const struct pipe_stream_output_info *so_info =
ilo_shader_get_kernel_so_info(ilo->vs);
@@ -1816,7 +1816,7 @@ gen6_pipeline_estimate_state_size(const struct ilo_3d_pipeline *p,
}
break;
case PIPE_SHADER_GEOMETRY:
if (ilo->gs && p->dev->gen == ILO_GEN(6)) {
if (ilo->gs && ilo_dev_gen(p->dev) == ILO_GEN(6)) {
const struct pipe_stream_output_info *so_info =
ilo_shader_get_kernel_so_info(ilo->gs);

29
src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c
View File

@@ -46,7 +46,8 @@ gen7_wa_pipe_control_cs_stall(struct ilo_3d_pipeline *p,
struct intel_bo *bo = NULL;
uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL;
assert(p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5));
assert(ilo_dev_gen(p->dev) == ILO_GEN(7) ||
ilo_dev_gen(p->dev) == ILO_GEN(7.5));
/* emit once */
if (p->state.has_gen6_wa_pipe_control)
@@ -94,7 +95,8 @@ gen7_wa_pipe_control_cs_stall(struct ilo_3d_pipeline *p,
static void
gen7_wa_pipe_control_vs_depth_stall(struct ilo_3d_pipeline *p)
{
assert(p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5));
assert(ilo_dev_gen(p->dev) == ILO_GEN(7) ||
ilo_dev_gen(p->dev) == ILO_GEN(7.5));
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 106:
@@ -115,7 +117,8 @@ static void
gen7_wa_pipe_control_wm_depth_stall(struct ilo_3d_pipeline *p,
bool change_depth_buffer)
{
assert(p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5));
assert(ilo_dev_gen(p->dev) == ILO_GEN(7) ||
ilo_dev_gen(p->dev) == ILO_GEN(7.5));
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 276:
@@ -163,7 +166,8 @@ gen7_wa_pipe_control_wm_depth_stall(struct ilo_3d_pipeline *p,
static void
gen7_wa_pipe_control_ps_max_threads_stall(struct ilo_3d_pipeline *p)
{
assert(p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5));
assert(ilo_dev_gen(p->dev) == ILO_GEN(7) ||
ilo_dev_gen(p->dev) == ILO_GEN(7.5));
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 286:
@@ -188,8 +192,8 @@ gen7_pipeline_common_urb(struct ilo_3d_pipeline *p,
/* 3DSTATE_URB_{VS,GS,HS,DS} */
if (DIRTY(VE) || DIRTY(VS)) {
/* the first 16KB are reserved for VS and PS PCBs */
const int offset =
(p->dev->gen == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
const int offset = (ilo_dev_gen(p->dev) == ILO_GEN(7.5) &&
p->dev->gt == 3) ? 32768 : 16384;
int vs_entry_size, vs_total_size;
vs_entry_size = (ilo->vs) ?
@@ -231,8 +235,8 @@ gen7_pipeline_common_pcb_alloc(struct ilo_3d_pipeline *p,
* Push constant buffers are only allowed to take up at most the first
* 16KB of the URB. Split the space evenly for VS and FS.
*/
const int max_size =
(p->dev->gen == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
const int max_size = (ilo_dev_gen(p->dev) == ILO_GEN(7.5) &&
p->dev->gt == 3) ? 32768 : 16384;
const int size = max_size / 2;
int offset = 0;
@@ -241,7 +245,7 @@ gen7_pipeline_common_pcb_alloc(struct ilo_3d_pipeline *p,
gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(&p->cp->builder, offset, size);
if (p->dev->gen == ILO_GEN(7))
if (ilo_dev_gen(p->dev) == ILO_GEN(7))
gen7_wa_pipe_control_cs_stall(p, true, true);
}
}
@@ -504,7 +508,8 @@ gen7_pipeline_wm(struct ilo_3d_pipeline *p,
const int num_samplers = ilo->sampler[PIPE_SHADER_FRAGMENT].count;
const bool dual_blend = ilo->blend->dual_blend;
if ((p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5)) &&
if ((ilo_dev_gen(p->dev) == ILO_GEN(7) ||
ilo_dev_gen(p->dev) == ILO_GEN(7.5)) &&
session->hw_ctx_changed)
gen7_wa_pipe_control_ps_max_threads_stall(p);
@@ -659,7 +664,7 @@ gen7_rectlist_pcb_alloc(struct ilo_3d_pipeline *p,
* 16KB of the URB. Split the space evenly for VS and FS.
*/
const int max_size =
(p->dev->gen == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
(ilo_dev_gen(p->dev) == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
const int size = max_size / 2;
int offset = 0;
@@ -678,7 +683,7 @@ gen7_rectlist_urb(struct ilo_3d_pipeline *p,
{
/* the first 16KB are reserved for VS and PS PCBs */
const int offset =
(p->dev->gen == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
(ilo_dev_gen(p->dev) == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
gen7_3DSTATE_URB_VS(&p->cp->builder, offset, p->dev->urb_size - offset,
blitter->ve.count * 4 * sizeof(float));

3
src/gallium/drivers/ilo/ilo_blitter_rectlist.c
View File

@@ -379,7 +379,8 @@ hiz_can_clear_zs(const struct ilo_blitter *blitter,
*/
switch (tex->layout.format) {
case PIPE_FORMAT_Z16_UNORM:
if (blitter->ilo->dev->gen == ILO_GEN(6) && tex->base.width0 % 16)
if (ilo_dev_gen(blitter->ilo->dev) == ILO_GEN(6) &&
tex->base.width0 % 16)
return false;
break;
case PIPE_FORMAT_Z24_UNORM_S8_UINT:

4
src/gallium/drivers/ilo/ilo_builder_decode.c
View File

@@ -213,7 +213,7 @@ writer_decode_sf_viewport(const struct ilo_builder *builder,
enum ilo_builder_writer_type which,
const struct ilo_builder_item *item)
{
if (builder->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
writer_decode_sf_clip_viewport_gen7(builder, which, item);
else
writer_decode_sf_viewport_gen6(builder, which, item);
@@ -453,7 +453,7 @@ writer_decode_surface(const struct ilo_builder *builder,
enum ilo_builder_writer_type which,
const struct ilo_builder_item *item)
{
if (builder->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
writer_decode_surface_gen7(builder, which, item);
else
writer_decode_surface_gen6(builder, which, item);

10
src/gallium/drivers/ilo/ilo_common.h
View File

@@ -76,13 +76,21 @@ struct ilo_dev_info {
bool has_timestamp;
bool has_gen7_sol_reset;
int gen;
/* use ilo_dev_gen() */
int gen_opaque;
int gt;
int urb_size;
};
extern int ilo_debug;
static inline int
ilo_dev_gen(const struct ilo_dev_info *dev)
{
return dev->gen_opaque;
}
/**
* Print a message, for dumping or debugging.
*/

19
src/gallium/drivers/ilo/ilo_format.c
View File

@@ -705,8 +705,12 @@ ilo_format_supports_rt(const struct ilo_dev_info *dev,
assert(!cap->rt_write_blending || cap->rt_write_blending >= cap->rt_write);
return util_format_is_pure_integer(format) ? (dev->gen >= cap->rt_write) :
(cap->rt_write_blending) ? (dev->gen >= cap->rt_write_blending) : false;
if (util_format_is_pure_integer(format))
return (ilo_dev_gen(dev) >= cap->rt_write);
else if (cap->rt_write_blending)
return (ilo_dev_gen(dev) >= cap->rt_write_blending);
else
return false;
}
static bool
@@ -722,8 +726,12 @@ ilo_format_supports_sampler(const struct ilo_dev_info *dev,
assert(!cap->filtering || cap->filtering >= cap->sampling);
return util_format_is_pure_integer(format) ? (dev->gen >= cap->sampling) :
(cap->filtering) ? (dev->gen >= cap->filtering) : false;
if (util_format_is_pure_integer(format))
return (ilo_dev_gen(dev) >= cap->sampling);
else if (cap->filtering)
return (ilo_dev_gen(dev) >= cap->filtering);
else
return false;
}
static bool
@@ -734,7 +742,8 @@ ilo_format_supports_vb(const struct ilo_dev_info *dev,
const struct ilo_vf_cap *cap = (idx >= 0 && idx < Elements(ilo_vf_caps)) ?
&ilo_vf_caps[idx] : NULL;
return (cap && cap->vertex_element && dev->gen >= cap->vertex_element);
return (cap && cap->vertex_element &&
ilo_dev_gen(dev) >= cap->vertex_element);
}
static boolean

2
src/gallium/drivers/ilo/ilo_format.h
View File

@@ -93,7 +93,7 @@ ilo_translate_format(const struct ilo_dev_info *dev,
}
break;
case PIPE_BIND_VERTEX_BUFFER:
if (dev->gen >= ILO_GEN(7.5))
if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
return ilo_translate_color_format(dev, format);
/*

12
src/gallium/drivers/ilo/ilo_gpe.h
View File

@@ -338,7 +338,7 @@ ilo_gpe_init_rasterizer(const struct ilo_dev_info *dev,
ilo_gpe_init_rasterizer_clip(dev, state, &rasterizer->clip);
ilo_gpe_init_rasterizer_sf(dev, state, &rasterizer->sf);
if (dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(dev) >= ILO_GEN(7))
ilo_gpe_init_rasterizer_wm_gen7(dev, state, &rasterizer->wm);
else
ilo_gpe_init_rasterizer_wm_gen6(dev, state, &rasterizer->wm);
@@ -417,7 +417,7 @@ ilo_gpe_init_view_surface_null(const struct ilo_dev_info *dev,
unsigned depth, unsigned level,
struct ilo_view_surface *surf)
{
if (dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
ilo_gpe_init_view_surface_null_gen7(dev,
width, height, depth, level, surf);
}
@@ -436,7 +436,7 @@ ilo_gpe_init_view_surface_for_buffer(const struct ilo_dev_info *dev,
bool is_rt, bool render_cache_rw,
struct ilo_view_surface *surf)
{
if (dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
ilo_gpe_init_view_surface_for_buffer_gen7(dev, buf, offset, size,
struct_size, elem_format, is_rt, render_cache_rw, surf);
}
@@ -457,7 +457,7 @@ ilo_gpe_init_view_surface_for_texture(const struct ilo_dev_info *dev,
bool is_rt,
struct ilo_view_surface *surf)
{
if (dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
ilo_gpe_init_view_surface_for_texture_gen7(dev, tex, format,
first_level, num_levels, first_layer, num_layers,
is_rt, surf);
@@ -496,7 +496,7 @@ ilo_gpe_init_gs_cso(const struct ilo_dev_info *dev,
const struct ilo_shader_state *gs,
struct ilo_shader_cso *cso)
{
if (dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
ilo_gpe_init_gs_cso_gen7(dev, gs, cso);
}
else {
@@ -519,7 +519,7 @@ ilo_gpe_init_fs_cso(const struct ilo_dev_info *dev,
const struct ilo_shader_state *fs,
struct ilo_shader_cso *cso)
{
if (dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
ilo_gpe_init_fs_cso_gen7(dev, fs, cso);
}
else {

32
src/gallium/drivers/ilo/ilo_gpe_gen6.c
View File

@@ -354,7 +354,7 @@ ilo_gpe_init_vs_cso(const struct ilo_dev_info *dev,
if (!vue_read_len)
vue_read_len = 1;
switch (dev->gen) {
switch (ilo_dev_gen(dev)) {
case ILO_GEN(6):
/*
* From the Sandy Bridge PRM, volume 1 part 1, page 22:
@@ -393,7 +393,7 @@ ilo_gpe_init_vs_cso(const struct ilo_dev_info *dev,
dw5 = GEN6_VS_DW5_STATISTICS |
GEN6_VS_DW5_VS_ENABLE;
if (dev->gen >= ILO_GEN(7.5))
if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
dw5 |= (max_threads - 1) << GEN75_VS_DW5_MAX_THREADS__SHIFT;
else
dw5 |= (max_threads - 1) << GEN6_VS_DW5_MAX_THREADS__SHIFT;
@@ -517,7 +517,7 @@ ilo_gpe_init_rasterizer_clip(const struct ilo_dev_info *dev,
dw1 = GEN6_CLIP_DW1_STATISTICS;
if (dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 219:
*
@@ -626,7 +626,7 @@ ilo_gpe_init_rasterizer_sf(const struct ilo_dev_info *dev,
GEN7_SF_DW1_VIEWPORT_ENABLE;
/* XXX GEN6 path seems to work fine for GEN7 */
if (false && dev->gen >= ILO_GEN(7)) {
if (false && ilo_dev_gen(dev) >= ILO_GEN(7)) {
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 258:
*
@@ -740,7 +740,7 @@ ilo_gpe_init_rasterizer_sf(const struct ilo_dev_info *dev,
dw2 |= line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT;
if (dev->gen >= ILO_GEN(7.5) && state->line_stipple_enable)
if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && state->line_stipple_enable)
dw2 |= GEN75_SF_DW2_LINE_STIPPLE_ENABLE;
if (state->scissor)
@@ -1006,7 +1006,7 @@ zs_init_info(const struct ilo_dev_info *dev,
info->surface_type = GEN6_SURFTYPE_2D;
}
if (dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
separate_stencil = true;
}
else {
@@ -1097,7 +1097,7 @@ zs_init_info(const struct ilo_dev_info *dev,
info->stencil.tiling = s8_tex->layout.tiling;
if (dev->gen == ILO_GEN(6)) {
if (ilo_dev_gen(dev) == ILO_GEN(6)) {
unsigned x, y;
assert(s8_tex->layout.walk == ILO_LAYOUT_WALK_LOD);
@@ -1115,7 +1115,7 @@ zs_init_info(const struct ilo_dev_info *dev,
info->hiz.tiling = INTEL_TILING_Y;
/* offset to the level */
if (dev->gen == ILO_GEN(6))
if (ilo_dev_gen(dev) == ILO_GEN(6))
info->hiz.offset = tex->layout.aux_offsets[level];
}
@@ -1136,8 +1136,8 @@ ilo_gpe_init_zs_surface(const struct ilo_dev_info *dev,
unsigned first_layer, unsigned num_layers,
struct ilo_zs_surface *zs)
{
const int max_2d_size = (dev->gen >= ILO_GEN(7)) ? 16384 : 8192;
const int max_array_size = (dev->gen >= ILO_GEN(7)) ? 2048 : 512;
const int max_2d_size = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 16384 : 8192;
const int max_array_size = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 2048 : 512;
struct ilo_zs_surface_info info;
uint32_t dw1, dw2, dw3, dw4, dw5, dw6;
@@ -1195,7 +1195,7 @@ ilo_gpe_init_zs_surface(const struct ilo_dev_info *dev,
dw2 = 0;
}
if (dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
if (info.zs.bo)
dw1 |= 1 << 28;
@@ -1260,7 +1260,7 @@ ilo_gpe_init_zs_surface(const struct ilo_dev_info *dev,
zs->payload[6] = info.stencil.stride - 1;
zs->payload[7] = info.stencil.offset;
if (dev->gen >= ILO_GEN(7.5))
if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
zs->payload[6] |= GEN75_STENCIL_DW1_STENCIL_BUFFER_ENABLE;
/* do not increment reference count */
@@ -1326,7 +1326,7 @@ viewport_get_guardband(const struct ilo_dev_info *dev,
* valid to the renderer, and those failing the XY clipping have a
* better chance of passing the GB test.
*/
const int max_extent = (dev->gen >= ILO_GEN(7)) ? 32768 : 16384;
const int max_extent = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 32768 : 16384;
const int half_len = 8192 / 2;
/* make sure the guardband is within the valid range */
@@ -1514,7 +1514,7 @@ ilo_gpe_init_blend(const struct ilo_dev_info *dev,
if (state->alpha_to_coverage) {
cso->dw_alpha_mod |= 1 << 31;
if (dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(dev) >= ILO_GEN(7))
cso->dw_alpha_mod |= 1 << 29;
}
@@ -2105,7 +2105,7 @@ ilo_gpe_init_sampler_cso(const struct ilo_dev_info *dev,
* With Gallium interface, Base is always zero and
* pipe_sampler_view::u.tex.first_level specifies SurfMinLod.
*/
if (dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
const float scale = 256.0f;
/* [-16.0, 16.0) in S4.8 */
@@ -2229,7 +2229,7 @@ ilo_gpe_init_sampler_cso(const struct ilo_dev_info *dev,
assert(mip_filter == GEN6_MIPFILTER_NONE);
}
if (dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
dw0 = 1 << 28 |
mip_filter << 20 |
lod_bias << 1;

43
src/gallium/drivers/ilo/ilo_gpe_gen6.h
View File

@@ -39,7 +39,8 @@
#include "ilo_gpe.h"
#define ILO_GPE_VALID_GEN(dev, min_gen, max_gen) \
assert((dev)->gen >= ILO_GEN(min_gen) && (dev)->gen <= ILO_GEN(max_gen))
assert(ilo_dev_gen(dev) >= ILO_GEN(min_gen) && \
ilo_dev_gen(dev) <= ILO_GEN(max_gen))
/**
* Translate winsys tiling to hardware tiling.
@@ -143,7 +144,7 @@ ilo_gpe_gen6_fill_3dstate_sf_raster(const struct ilo_dev_info *dev,
payload[5] = 0;
}
if (dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
int format;
/* separate stencil */
@@ -254,7 +255,7 @@ gen6_MI_STORE_DATA_IMM(struct ilo_builder *builder,
assert(bo_offset % ((store_qword) ? 8 : 4) == 0);
/* must use GGTT on GEN6 as in PIPE_CONTROL */
if (builder->dev->gen == ILO_GEN(6)) {
if (ilo_dev_gen(builder->dev) == ILO_GEN(6)) {
dw0 |= GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT;
reloc_flags |= INTEL_RELOC_GGTT;
}
@@ -306,7 +307,7 @@ gen6_MI_STORE_REGISTER_MEM(struct ilo_builder *builder,
assert(reg % 4 == 0 && bo_offset % 4 == 0);
/* must use GGTT on GEN6 as in PIPE_CONTROL */
if (builder->dev->gen == ILO_GEN(6)) {
if (ilo_dev_gen(builder->dev) == ILO_GEN(6)) {
dw0 |= GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT;
reloc_flags |= INTEL_RELOC_GGTT;
}
@@ -335,7 +336,7 @@ gen6_MI_REPORT_PERF_COUNT(struct ilo_builder *builder,
assert(bo_offset % 64 == 0);
/* must use GGTT on GEN6 as in PIPE_CONTROL */
if (builder->dev->gen == ILO_GEN(6)) {
if (ilo_dev_gen(builder->dev) == ILO_GEN(6)) {
bo_offset |= GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT;
reloc_flags |= INTEL_RELOC_GGTT;
}
@@ -719,7 +720,7 @@ gen6_3DSTATE_VERTEX_BUFFERS(struct ilo_builder *builder,
else
dw[0] |= GEN6_VB_STATE_DW0_ACCESS_VERTEXDATA;
if (builder->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
dw[0] |= GEN7_VB_STATE_DW0_ADDR_MODIFIED;
/* use null vb if there is no buffer or the stride is out of range */
@@ -909,7 +910,7 @@ gen6_3DSTATE_INDEX_BUFFER(struct ilo_builder *builder,
return;
/* this is moved to the new 3DSTATE_VF */
if (builder->dev->gen >= ILO_GEN(7.5))
if (ilo_dev_gen(builder->dev) >= ILO_GEN(7.5))
assert(!enable_cut_index);
switch (ib->hw_index_size) {
@@ -1426,7 +1427,7 @@ gen6_3DSTATE_DRAWING_RECTANGLE(struct ilo_builder *builder,
ILO_GPE_VALID_GEN(builder->dev, 6, 7.5);
if (builder->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) {
rect_limit = 16383;
}
else {
@@ -1470,7 +1471,7 @@ zs_align_surface(const struct ilo_dev_info *dev,
ILO_GPE_VALID_GEN(dev, 6, 7.5);
if (dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
shift_w = 4;
shift_h = 18;
mask = 0x3fff;
@@ -1504,7 +1505,7 @@ gen6_3DSTATE_DEPTH_BUFFER(struct ilo_builder *builder,
ILO_GPE_VALID_GEN(builder->dev, 6, 7.5);
dw0 = (builder->dev->gen >= ILO_GEN(7)) ?
dw0 = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
GEN7_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER) :
GEN6_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER);
dw0 |= (cmd_len - 2);
@@ -1583,7 +1584,7 @@ gen6_3DSTATE_LINE_STIPPLE(struct ilo_builder *builder,
dw[0] = dw0;
dw[1] = pattern;
if (builder->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) {
/* in U1.16 */
inverse = (unsigned) (65536.0f / factor);
dw[2] = inverse << 15 | factor;
@@ -1642,7 +1643,7 @@ gen6_3DSTATE_MULTISAMPLE(struct ilo_builder *builder,
const uint32_t *packed_sample_pos,
bool pixel_location_center)
{
const uint8_t cmd_len = (builder->dev->gen >= ILO_GEN(7)) ? 4 : 3;
const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ? 4 : 3;
const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_MULTISAMPLE) |
(cmd_len - 2);
uint32_t dw1, dw2, dw3, *dw;
@@ -1665,7 +1666,7 @@ gen6_3DSTATE_MULTISAMPLE(struct ilo_builder *builder,
dw3 = 0;
break;
case 8:
assert(builder->dev->gen >= ILO_GEN(7));
assert(ilo_dev_gen(builder->dev) >= ILO_GEN(7));
dw1 |= GEN7_MULTISAMPLE_DW1_NUMSAMPLES_8;
dw2 = packed_sample_pos[0];
dw3 = packed_sample_pos[1];
@@ -1682,7 +1683,7 @@ gen6_3DSTATE_MULTISAMPLE(struct ilo_builder *builder,
dw[0] = dw0;
dw[1] = dw1;
dw[2] = dw2;
if (builder->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
dw[2] = dw3;
}
@@ -1696,7 +1697,7 @@ gen6_3DSTATE_STENCIL_BUFFER(struct ilo_builder *builder,
ILO_GPE_VALID_GEN(builder->dev, 6, 7.5);
dw0 = (builder->dev->gen >= ILO_GEN(7)) ?
dw0 = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
GEN7_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER) :
GEN6_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER);
dw0 |= (cmd_len - 2);
@@ -1724,7 +1725,7 @@ gen6_3DSTATE_HIER_DEPTH_BUFFER(struct ilo_builder *builder,
ILO_GPE_VALID_GEN(builder->dev, 6, 7.5);
dw0 = (builder->dev->gen >= ILO_GEN(7)) ?
dw0 = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
GEN7_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER) :
GEN6_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER);
dw0 |= (cmd_len - 2);
@@ -1808,7 +1809,7 @@ gen6_PIPE_CONTROL(struct ilo_builder *builder,
GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT |
GEN6_PIPE_CONTROL_WRITE_TIMESTAMP;
if (builder->dev->gen == ILO_GEN(6))
if (ilo_dev_gen(builder->dev) == ILO_GEN(6))
bit_test |= GEN6_PIPE_CONTROL_NOTIFY_ENABLE;
assert(dw1 & bit_test);
@@ -1836,7 +1837,7 @@ gen6_PIPE_CONTROL(struct ilo_builder *builder,
* The kernel will add the mapping automatically (when write domain is
* INTEL_DOMAIN_INSTRUCTION).
*/
if (builder->dev->gen == ILO_GEN(6) && bo) {
if (ilo_dev_gen(builder->dev) == ILO_GEN(6) && bo) {
bo_offset |= GEN6_PIPE_CONTROL_DW2_USE_GGTT;
reloc_flags |= INTEL_RELOC_GGTT;
}
@@ -2270,7 +2271,7 @@ gen6_SURFACE_STATE(struct ilo_builder *builder,
bool for_render)
{
const int state_align = 32;
const int state_len = (builder->dev->gen >= ILO_GEN(7)) ? 8 : 6;
const int state_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ? 8 : 6;
uint32_t state_offset;
ILO_GPE_VALID_GEN(builder->dev, 6, 7.5);
@@ -2409,7 +2410,7 @@ gen6_SAMPLER_STATE(struct ilo_builder *builder,
dw[0] |= dw_filter;
if (builder->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) {
dw[3] |= dw_wrap;
}
else {
@@ -2441,7 +2442,7 @@ gen6_SAMPLER_BORDER_COLOR_STATE(struct ilo_builder *builder,
const struct ilo_sampler_cso *sampler)
{
const int state_align = 32;
const int state_len = (builder->dev->gen >= ILO_GEN(7)) ? 4 : 12;
const int state_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ? 4 : 12;
ILO_GPE_VALID_GEN(builder->dev, 6, 7.5);

8
src/gallium/drivers/ilo/ilo_gpe_gen7.c
View File

@@ -49,7 +49,7 @@ ilo_gpe_init_gs_cso_gen7(const struct ilo_dev_info *dev,
/* in pairs */
vue_read_len = (vue_read_len + 1) / 2;
switch (dev->gen) {
switch (ilo_dev_gen(dev)) {
case ILO_GEN(7.5):
max_threads = (dev->gt >= 2) ? 256 : 70;
break;
@@ -143,7 +143,7 @@ ilo_gpe_init_fs_cso_gen7(const struct ilo_dev_info *dev,
dw4 = GEN7_PS_DW4_POSOFFSET_NONE;
/* see brwCreateContext() */
switch (dev->gen) {
switch (ilo_dev_gen(dev)) {
case ILO_GEN(7.5):
max_threads = (dev->gt == 3) ? 408 : (dev->gt == 2) ? 204 : 102;
dw4 |= (max_threads - 1) << GEN75_PS_DW4_MAX_THREADS__SHIFT;
@@ -411,7 +411,7 @@ ilo_gpe_init_view_surface_for_buffer_gen7(const struct ilo_dev_info *dev,
dw[6] = 0;
dw[7] = 0;
if (dev->gen >= ILO_GEN(7.5)) {
if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
dw[7] |= GEN_SHIFT32(GEN75_SCS_RED, GEN75_SURFACE_DW7_SCS_R) |
GEN_SHIFT32(GEN75_SCS_GREEN, GEN75_SURFACE_DW7_SCS_G) |
GEN_SHIFT32(GEN75_SCS_BLUE, GEN75_SURFACE_DW7_SCS_B) |
@@ -624,7 +624,7 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev,
dw[6] = 0;
dw[7] = 0;
if (dev->gen >= ILO_GEN(7.5)) {
if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
dw[7] |= GEN_SHIFT32(GEN75_SCS_RED, GEN75_SURFACE_DW7_SCS_R) |
GEN_SHIFT32(GEN75_SCS_GREEN, GEN75_SURFACE_DW7_SCS_G) |
GEN_SHIFT32(GEN75_SCS_BLUE, GEN75_SURFACE_DW7_SCS_B) |

6
src/gallium/drivers/ilo/ilo_gpe_gen7.h
View File

@@ -514,7 +514,7 @@ gen7_3DSTATE_PS(struct ilo_builder *builder,
dw4 = GEN7_PS_DW4_8_PIXEL_DISPATCH;
/* see brwCreateContext() */
switch (builder->dev->gen) {
switch (ilo_dev_gen(builder->dev)) {
case ILO_GEN(7.5):
max_threads = (builder->dev->gt == 3) ? 408 :
(builder->dev->gt == 2) ? 204 : 102;
@@ -730,7 +730,7 @@ gen7_3dstate_urb(struct ilo_builder *builder,
switch (subop) {
case GEN7_RENDER_OPCODE_3DSTATE_URB_VS:
switch (builder->dev->gen) {
switch (ilo_dev_gen(builder->dev)) {
case ILO_GEN(7.5):
max_entries = (builder->dev->gt >= 2) ? 1664 : 640;
min_entries = (builder->dev->gt >= 2) ? 64 : 32;
@@ -756,7 +756,7 @@ gen7_3dstate_urb(struct ilo_builder *builder,
assert(num_entries >= 138);
break;
case GEN7_RENDER_OPCODE_3DSTATE_URB_GS:
switch (builder->dev->gen) {
switch (ilo_dev_gen(builder->dev)) {
case ILO_GEN(7.5):
max_entries = (builder->dev->gt >= 2) ? 640 : 256;
break;

26
src/gallium/drivers/ilo/ilo_layout.c
View File

@@ -214,9 +214,9 @@ layout_init_layer_height(struct ilo_layout *layout,
* QPitch by 4.
*/
layout->layer_height = params->h0 + params->h1 +
((params->dev->gen >= ILO_GEN(7)) ? 12 : 11) * layout->align_j;
((ilo_dev_gen(params->dev) >= ILO_GEN(7)) ? 12 : 11) * layout->align_j;
if (params->dev->gen == ILO_GEN(6) && templ->nr_samples > 1 &&
if (ilo_dev_gen(params->dev) == ILO_GEN(6) && templ->nr_samples > 1 &&
layout->height0 % 4 == 1)
layout->layer_height += 4;
@@ -395,7 +395,7 @@ layout_init_alignments(struct ilo_layout *layout,
layout->align_i = layout->block_width;
layout->align_j = layout->block_height;
} else if (templ->bind & PIPE_BIND_DEPTH_STENCIL) {
if (params->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(params->dev) >= ILO_GEN(7)) {
switch (layout->format) {
case PIPE_FORMAT_Z16_UNORM:
layout->align_i = 8;
@@ -424,7 +424,7 @@ layout_init_alignments(struct ilo_layout *layout,
}
} else {
const bool valign_4 = (templ->nr_samples > 1) ||
(params->dev->gen >= ILO_GEN(7) &&
(ilo_dev_gen(params->dev) >= ILO_GEN(7) &&
layout->tiling == INTEL_TILING_Y &&
(templ->bind & PIPE_BIND_RENDER_TARGET));
@@ -518,7 +518,7 @@ layout_get_valid_tilings(const struct ilo_layout *layout,
*
* "VALIGN_4 is not supported for surface format R32G32B32_FLOAT."
*/
if (params->dev->gen >= ILO_GEN(7) && layout->block_size == 12)
if (ilo_dev_gen(params->dev) >= ILO_GEN(7) && layout->block_size == 12)
valid_tilings &= ~LAYOUT_TILING_Y;
}
@@ -642,7 +642,7 @@ static void
layout_init_walk(struct ilo_layout *layout,
struct ilo_layout_params *params)
{
if (params->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(params->dev) >= ILO_GEN(7))
layout_init_walk_gen7(layout, params);
else
layout_init_walk_gen6(layout, params);
@@ -668,7 +668,7 @@ layout_init_size_and_format(struct ilo_layout *layout,
* GEN7+ requires separate stencil buffers.
*/
if (templ->bind & PIPE_BIND_DEPTH_STENCIL) {
if (params->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(params->dev) >= ILO_GEN(7))
require_separate_stencil = true;
else
require_separate_stencil = (layout->aux == ILO_LAYOUT_AUX_HIZ);
@@ -710,7 +710,7 @@ layout_want_mcs(struct ilo_layout *layout,
bool want_mcs = false;
/* MCS is for RT on GEN7+ */
if (params->dev->gen < ILO_GEN(7))
if (ilo_dev_gen(params->dev) < ILO_GEN(7))
return false;
if (templ->target != PIPE_TEXTURE_2D ||
@@ -790,7 +790,7 @@ layout_want_hiz(const struct ilo_layout *layout,
* format is PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, enabling and disabling HiZ
* can result in incompatible formats.
*/
if (params->dev->gen == ILO_GEN(6) &&
if (ilo_dev_gen(params->dev) == ILO_GEN(6) &&
templ->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
templ->last_level)
return false;
@@ -897,7 +897,7 @@ layout_calculate_bo_size(struct ilo_layout *layout,
* at the bottom of the surface. This is in addition to the padding
* required above."
*/
if (params->dev->gen >= ILO_GEN(7.5) &&
if (ilo_dev_gen(params->dev) >= ILO_GEN(7.5) &&
(params->templ->bind & PIPE_BIND_SAMPLER_VIEW) &&
layout->tiling == INTEL_TILING_NONE) {
layout->bo_height +=
@@ -1014,7 +1014,7 @@ layout_calculate_hiz_size(struct ilo_layout *layout,
*
* We will put all LODs in a single bo with ILO_LAYOUT_WALK_LOD.
*/
if (params->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(params->dev) >= ILO_GEN(7))
hz_walk = layout->walk;
else
hz_walk = ILO_LAYOUT_WALK_LOD;
@@ -1076,13 +1076,13 @@ layout_calculate_hiz_size(struct ilo_layout *layout,
const unsigned h0 = align(params->h0, hz_align_j);
const unsigned h1 = align(params->h1, hz_align_j);
const unsigned htail =
((params->dev->gen >= ILO_GEN(7)) ? 12 : 11) * hz_align_j;
((ilo_dev_gen(params->dev) >= ILO_GEN(7)) ? 12 : 11) * hz_align_j;
const unsigned hz_qpitch = h0 + h1 + htail;
hz_width = align(layout->lods[0].slice_width, 16);
hz_height = hz_qpitch * templ->array_size / 2;
if (params->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(params->dev) >= ILO_GEN(7))
hz_height = align(hz_height, 8);
}
break;

5
src/gallium/drivers/ilo/ilo_resource.c
View File

@@ -267,7 +267,8 @@ tex_alloc_bos(struct ilo_texture *tex,
case ILO_LAYOUT_AUX_HIZ:
if (!tex_create_hiz(tex)) {
/* Separate Stencil Buffer requires HiZ to be enabled */
if (is->dev.gen == ILO_GEN(6) && tex->layout.separate_stencil)
if (ilo_dev_gen(&is->dev) == ILO_GEN(6) &&
tex->layout.separate_stencil)
return false;
}
break;
@@ -398,7 +399,7 @@ buf_create(struct pipe_screen *screen, const struct pipe_resource *templ)
buf->bo_size = align(buf->bo_size, 256) + 16;
if ((templ->bind & PIPE_BIND_VERTEX_BUFFER) &&
is->dev.gen < ILO_GEN(7.5)) {
ilo_dev_gen(&is->dev) < ILO_GEN(7.5)) {
/*
* As noted in ilo_translate_format(), we treat some 3-component formats
* as 4-component formats to work around hardware limitations. Imagine

16
src/gallium/drivers/ilo/ilo_screen.c
View File

@@ -310,18 +310,18 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
* GEN6 8192x8192x512 2048x2048x2048
* GEN7 16384x16384x2048 2048x2048x2048
*/
return (is->dev.gen >= ILO_GEN(7)) ? 15 : 14;
return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
return 12;
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
return (is->dev.gen >= ILO_GEN(7)) ? 15 : 14;
return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 15 : 14;
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
return false;
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_SM3:
return true;
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
if (is->dev.gen >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
if (ilo_dev_gen(&is->dev) >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
return 0;
return ILO_MAX_SO_BUFFERS;
case PIPE_CAP_PRIMITIVE_RESTART:
@@ -330,7 +330,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_INDEP_BLEND_FUNC:
return true;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
return (is->dev.gen >= ILO_GEN(7)) ? 2048 : 512;
return (ilo_dev_gen(&is->dev) >= ILO_GEN(7)) ? 2048 : 512;
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
@@ -363,7 +363,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
return ILO_MAX_SO_BINDINGS;
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
if (is->dev.gen >= ILO_GEN(7))
if (ilo_dev_gen(&is->dev) >= ILO_GEN(7))
return is->dev.has_gen7_sol_reset;
else
return false; /* TODO */
@@ -690,18 +690,18 @@ init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
*/
if (gen_is_hsw(info->devid)) {
dev->gen = ILO_GEN(7.5);
dev->gen_opaque = ILO_GEN(7.5);
dev->gt = gen_get_hsw_gt(info->devid);
dev->urb_size = ((dev->gt == 3) ? 512 :
(dev->gt == 2) ? 256 : 128) * 1024;
}
else if (gen_is_ivb(info->devid) || gen_is_vlv(info->devid)) {
dev->gen = ILO_GEN(7);
dev->gen_opaque = ILO_GEN(7);
dev->gt = (gen_is_ivb(info->devid)) ? gen_get_ivb_gt(info->devid) : 1;
dev->urb_size = ((dev->gt == 2) ? 256 : 128) * 1024;
}
else if (gen_is_snb(info->devid)) {
dev->gen = ILO_GEN(6);
dev->gen_opaque = ILO_GEN(6);
dev->gt = gen_get_snb_gt(info->devid);
dev->urb_size = ((dev->gt == 2) ? 64 : 32) * 1024;
}

4
src/gallium/drivers/ilo/ilo_shader.c
View File

@@ -828,8 +828,8 @@ ilo_shader_select_kernel_routing(struct ilo_shader_state *shader,
int dst_len, dst_slot;
/* we are constructing 3DSTATE_SBE here */
assert(shader->info.dev->gen >= ILO_GEN(6) &&
shader->info.dev->gen <= ILO_GEN(7.5));
assert(ilo_dev_gen(shader->info.dev) >= ILO_GEN(6) &&
ilo_dev_gen(shader->info.dev) <= ILO_GEN(7.5));
assert(kernel);

2
src/gallium/drivers/ilo/ilo_transfer.c
View File

@@ -96,7 +96,7 @@ resource_get_transfer_method(struct pipe_resource *res,
/* we may need to convert on the fly */
if (tex->separate_s8 || tex->layout.format == PIPE_FORMAT_S8_UINT) {
/* on GEN6, separate stencil is enabled only when HiZ is */
if (is->dev.gen >= ILO_GEN(7) ||
if (ilo_dev_gen(&is->dev) >= ILO_GEN(7) ||
ilo_texture_can_enable_hiz(tex, transfer->level,
transfer->box.z, transfer->box.depth)) {
m = ILO_TRANSFER_MAP_SW_ZS;

8
src/gallium/drivers/ilo/shader/ilo_shader_fs.c
View File

@@ -494,7 +494,7 @@ fs_lower_opcode_tgsi_direct(struct fs_compile_context *fcc,
fs_lower_opcode_tgsi_in(fcc, inst->dst, dim, idx);
break;
case TOY_OPCODE_TGSI_CONST:
if (tc->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7))
fs_lower_opcode_tgsi_const_gen7(fcc, inst->dst, dim, inst->src[1]);
else
fs_lower_opcode_tgsi_const_gen6(fcc, inst->dst, dim, inst->src[1]);
@@ -801,7 +801,7 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
msg_type = GEN7_MSG_SAMPLER_SAMPLE_D_C;
ref_or_si = coords[ref_pos];
if (tc->dev->gen < ILO_GEN(7.5))
if (ilo_dev_gen(tc->dev) < ILO_GEN(7.5))
tc_fail(tc, "TXD with shadow sampler not supported");
}
else {
@@ -1064,7 +1064,7 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
}
/* set up sampler parameters */
if (tc->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
msg_len = fs_add_sampler_params_gen7(tc, msg_type, base_mrf, param_size,
coords, num_coords, bias_or_lod, ref_or_si, ddx, ddy, num_derivs);
}
@@ -1849,7 +1849,7 @@ fs_setup(struct fs_compile_context *fcc,
fcc->num_grf_per_vrf =
(fcc->dispatch_mode == GEN6_WM_DW5_16_PIXEL_DISPATCH) ? 2 : 1;
if (fcc->tc.dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(fcc->tc.dev) >= ILO_GEN(7)) {
fcc->last_free_grf -= 15;
fcc->first_free_mrf = fcc->last_free_grf + 1;
fcc->last_free_mrf = fcc->first_free_mrf + 14;

16
src/gallium/drivers/ilo/shader/ilo_shader_vs.c
View File

@@ -244,7 +244,7 @@ vs_lower_opcode_tgsi_direct(struct vs_compile_context *vcc,
vs_lower_opcode_tgsi_in(vcc, inst->dst, dim, idx);
break;
case TOY_OPCODE_TGSI_CONST:
if (tc->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7))
vs_lower_opcode_tgsi_const_gen7(vcc, inst->dst, dim, inst->src[1]);
else
vs_lower_opcode_tgsi_const_gen6(vcc, inst->dst, dim, inst->src[1]);
@@ -298,7 +298,7 @@ vs_lower_opcode_tgsi_indirect(struct vs_compile_context *vcc,
indirect_idx = tsrc_from(tmp);
}
if (tc->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7))
vs_lower_opcode_tgsi_const_gen7(vcc, inst->dst, dim, indirect_idx);
else
vs_lower_opcode_tgsi_const_gen6(vcc, inst->dst, dim, indirect_idx);
@@ -363,7 +363,7 @@ vs_add_sampler_params(struct toy_compiler *tc, int msg_type, int base_mrf,
assert(num_coords <= 3);
tc_MOV(tc, tdst_writemask(tdst_d(m[0]), coords_writemask), coords);
tc_MOV(tc, tdst_writemask(tdst_d(m[0]), TOY_WRITEMASK_W), bias_or_lod);
if (tc->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
num_params = 4;
}
else {
@@ -417,7 +417,7 @@ vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst,
msg_type = GEN7_MSG_SAMPLER_SAMPLE_D_C;
ref_or_si = tsrc_swizzle1(coords, ref_pos);
if (tc->dev->gen < ILO_GEN(7.5))
if (ilo_dev_gen(tc->dev) < ILO_GEN(7.5))
tc_fail(tc, "TXD with shadow sampler not supported");
}
else {
@@ -917,7 +917,7 @@ vs_write_vue(struct vs_compile_context *vcc)
inst = tc_MOV(tc, header, r0);
inst->mask_ctrl = GEN6_MASKCTRL_NOMASK;
if (tc->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
inst = tc_OR(tc, tdst_offset(header, 0, 5),
tsrc_rect(tsrc_offset(r0, 0, 5), TOY_RECT_010),
tsrc_rect(tsrc_imm_ud(0xff00), TOY_RECT_010));
@@ -955,7 +955,7 @@ vs_write_vue(struct vs_compile_context *vcc)
eot = false;
}
if (tc->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
/* do not forget about the header */
msg_len = 1 + num_attrs;
}
@@ -1273,7 +1273,7 @@ vs_setup(struct vs_compile_context *vcc,
vcc->num_grf_per_vrf = 1;
if (vcc->tc.dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(vcc->tc.dev) >= ILO_GEN(7)) {
vcc->last_free_grf -= 15;
vcc->first_free_mrf = vcc->last_free_grf + 1;
vcc->last_free_mrf = vcc->first_free_mrf + 14;
@@ -1299,7 +1299,7 @@ ilo_shader_compile_vs(const struct ilo_shader_state *state,
if (!vs_setup(&vcc, state, variant))
return NULL;
if (vcc.tc.dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(vcc.tc.dev) >= ILO_GEN(7)) {
need_gs = false;
}
else {

27
src/gallium/drivers/ilo/shader/toy_compiler_disasm.c
View File

@@ -188,7 +188,7 @@ disasm_inst_decode_dw0_gen6(struct disasm_inst *inst, uint32_t dw0)
switch (inst->opcode) {
case GEN6_OPCODE_IF:
inst->has_jip = true;
inst->has_uip = (inst->dev->gen >= ILO_GEN(7));
inst->has_uip = (ilo_dev_gen(inst->dev) >= ILO_GEN(7));
break;
case GEN6_OPCODE_BREAK:
case GEN6_OPCODE_CONT:
@@ -244,7 +244,8 @@ disasm_inst_decode_dw0_gen6(struct disasm_inst *inst, uint32_t dw0)
static bool
disasm_inst_jip_in_dw1_high_gen6(const struct disasm_inst *inst)
{
return (inst->dev->gen == ILO_GEN(6) && inst->has_jip && !inst->has_uip);
return (ilo_dev_gen(inst->dev) == ILO_GEN(6) &&
inst->has_jip && !inst->has_uip);
}
static void
@@ -257,7 +258,7 @@ disasm_inst_decode_dw1_gen6(struct disasm_inst *inst, uint32_t dw1)
inst->src1.base.file = GEN_EXTRACT(dw1, GEN6_INST_SRC1_FILE);
inst->src1.base.type = GEN_EXTRACT(dw1, GEN6_INST_SRC1_TYPE);
if (inst->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(inst->dev) >= ILO_GEN(7))
inst->nib_ctrl = (bool) (dw1 & GEN7_INST_NIBCTRL);
if (disasm_inst_jip_in_dw1_high_gen6(inst)) {
@@ -303,7 +304,7 @@ disasm_inst_decode_dw2_dw3_gen6(struct disasm_inst *inst,
{
int count, i;
if (inst->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(inst->dev) >= ILO_GEN(7))
inst->flag_reg = GEN_EXTRACT(dw2, GEN7_INST_FLAG_REG);
inst->flag_subreg = GEN_EXTRACT(dw2, GEN6_INST_FLAG_SUBREG);
@@ -381,7 +382,7 @@ disasm_inst_decode_3src_dw1_gen6(struct disasm_inst *inst, uint32_t dw1)
inst->flag_subreg = GEN_EXTRACT(dw1, GEN6_3SRC_FLAG_SUBREG);
if (inst->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(inst->dev) >= ILO_GEN(7)) {
inst->nib_ctrl = (bool) (dw1 & GEN7_3SRC_NIBCTRL);
inst->flag_reg = GEN_EXTRACT(dw1, GEN7_3SRC_FLAG_REG);
@@ -1162,7 +1163,7 @@ disasm_printer_add_mdesc_sampler(struct disasm_printer *printer,
{
int op, simd;
if (inst->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(inst->dev) >= ILO_GEN(7)) {
op = GEN_EXTRACT(mdesc, GEN7_MSG_SAMPLER_OP);
simd = GEN_EXTRACT(mdesc, GEN7_MSG_SAMPLER_SIMD);
} {
@@ -1185,7 +1186,7 @@ disasm_printer_add_mdesc_urb(struct disasm_printer *printer,
int offset;
bool interleaved, complete, allocate, used;
if (inst->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(inst->dev) >= ILO_GEN(7)) {
switch (GEN_EXTRACT(mdesc, GEN7_MSG_URB_OP)) {
case GEN7_MSG_URB_WRITE_HWORD: op = "write HWord"; break;
case GEN7_MSG_URB_WRITE_OWORD: op = "write OWord"; break;
@@ -1229,9 +1230,9 @@ disasm_printer_add_mdesc_dp_sampler(struct disasm_printer *printer,
const struct disasm_inst *inst,
uint32_t mdesc)
{
const int op = (inst->dev->gen >= ILO_GEN(7)) ?
const int op = (ilo_dev_gen(inst->dev) >= ILO_GEN(7)) ?
GEN_EXTRACT(mdesc, GEN7_MSG_DP_OP) : GEN_EXTRACT(mdesc, GEN6_MSG_DP_OP);
const bool write_commit = (inst->dev->gen == ILO_GEN(6)) ?
const bool write_commit = (ilo_dev_gen(inst->dev) == ILO_GEN(6)) ?
(mdesc & GEN6_MSG_DP_SEND_WRITE_COMMIT) : 0;
disasm_printer_add(printer, " (%d, %d, %d, %d)",
@@ -1245,12 +1246,12 @@ disasm_printer_add_mdesc_dp_rc(struct disasm_printer *printer,
const struct disasm_inst *inst,
uint32_t mdesc)
{
const int op = (inst->dev->gen >= ILO_GEN(7)) ?
const int op = (ilo_dev_gen(inst->dev) >= ILO_GEN(7)) ?
GEN_EXTRACT(mdesc, GEN7_MSG_DP_OP) : GEN_EXTRACT(mdesc, GEN6_MSG_DP_OP);
const char *str;
bool is_rt_write;
if (inst->dev->gen >= ILO_GEN(7.5)) {
if (ilo_dev_gen(inst->dev) >= ILO_GEN(7.5)) {
switch (op) {
case GEN75_MSG_DP_RC_MEDIA_BLOCK_READ: str = "media block read"; break;
case GEN75_MSG_DP_RC_MEMORY_FENCE: str = "memory fence"; break;
@@ -1260,7 +1261,7 @@ disasm_printer_add_mdesc_dp_rc(struct disasm_printer *printer,
}
is_rt_write = (op == GEN75_MSG_DP_RC_RT_WRITE);
} else if (inst->dev->gen >= ILO_GEN(7)) {
} else if (ilo_dev_gen(inst->dev) >= ILO_GEN(7)) {
switch (op) {
case GEN7_MSG_DP_RC_MEDIA_BLOCK_READ: str = "media block read"; break;
case GEN7_MSG_DP_RC_TYPED_SURFACE_READ: str = "typed surface read"; break;
@@ -1311,7 +1312,7 @@ disasm_printer_add_mdesc_dp_rc(struct disasm_printer *printer,
disasm_printer_add(printer, " %s%s%s%s", str,
(mdesc & GEN6_MSG_DP_SLOTGRP_HI) ? " Hi" : "",
(mdesc & GEN6_MSG_DP_RT_LAST) ? " LastRT" : "",
(inst->dev->gen == ILO_GEN(6) &&
(ilo_dev_gen(inst->dev) == ILO_GEN(6) &&
(mdesc & GEN6_MSG_DP_SEND_WRITE_COMMIT)) ? " WriteCommit" : "");
}

8
src/gallium/drivers/ilo/shader/toy_helpers.h
View File

@@ -168,7 +168,7 @@ tsrc_imm_mdesc_sampler(const struct toy_compiler *tc,
assert(sampler_index < 16);
assert(binding_table_index < 256);
if (tc->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
ctrl = simd_mode << 17 |
message_type << 12 |
sampler_index << 8 |
@@ -198,7 +198,7 @@ tsrc_imm_mdesc_data_port(const struct toy_compiler *tc,
{
uint32_t ctrl;
if (tc->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
assert(!send_write_commit_message);
assert((message_specific_control & 0x3f00) == message_specific_control);
@@ -235,7 +235,7 @@ tsrc_imm_mdesc_data_port_scratch(const struct toy_compiler *tc,
const bool header_present = true;
uint32_t ctrl;
assert(tc->dev->gen >= ILO_GEN(7));
assert(ilo_dev_gen(tc->dev) >= ILO_GEN(7));
assert(num_registers == 1 || num_registers == 2 || num_registers == 4);
ctrl = 1 << 18 |
@@ -264,7 +264,7 @@ tsrc_imm_mdesc_urb(const struct toy_compiler *tc,
const bool header_present = true;
uint32_t ctrl;
if (tc->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
const bool per_slot_offset = false;
ctrl = per_slot_offset << 16 |

17
src/gallium/drivers/ilo/shader/toy_legalize.c
View File

@@ -335,7 +335,7 @@ patch_while_jip(struct toy_compiler *tc, struct toy_inst *inst)
dist--;
}
if (tc->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7))
inst->src[1] = tsrc_imm_w(dist * 2);
else
inst->dst = tdst_imm_w(dist * 2);
@@ -375,7 +375,7 @@ patch_if_else_jip(struct toy_compiler *tc, struct toy_inst *inst)
/* the following instruction */
jip = (dist + 1) * 2;
if (tc->dev->gen == ILO_GEN(6)) {
if (ilo_dev_gen(tc->dev) == ILO_GEN(6)) {
uip = jip;
break;
}
@@ -388,7 +388,7 @@ patch_if_else_jip(struct toy_compiler *tc, struct toy_inst *inst)
dist++;
}
if (tc->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
/* what should the type be? */
inst->dst.type = TOY_TYPE_D;
inst->src[0].type = TOY_TYPE_D;
@@ -433,7 +433,7 @@ patch_endif_jip(struct toy_compiler *tc, struct toy_inst *inst)
if (!found)
dist = 1;
if (tc->dev->gen >= ILO_GEN(7))
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7))
inst->src[1] = tsrc_imm_w(dist * 2);
else
inst->dst = tdst_imm_w(dist * 2);
@@ -485,7 +485,8 @@ patch_break_continue_jip(struct toy_compiler *tc, struct toy_inst *inst)
}
else {
/* the following instruction */
if (tc->dev->gen == ILO_GEN(6) && inst->opcode == GEN6_OPCODE_BREAK)
if (ilo_dev_gen(tc->dev) == ILO_GEN(6) &&
inst->opcode == GEN6_OPCODE_BREAK)
dist++;
uip = dist * 2;
@@ -546,7 +547,7 @@ toy_compiler_legalize_for_asm(struct toy_compiler *tc)
*
* "INT DIV function does not support SIMD16."
*/
if (tc->dev->gen < ILO_GEN(7) ||
if (ilo_dev_gen(tc->dev) < ILO_GEN(7) ||
inst->cond_modifier == GEN6_MATH_INT_DIV_QUOTIENT ||
inst->cond_modifier == GEN6_MATH_INT_DIV_REMAINDER) {
struct toy_inst *inst2;
@@ -566,7 +567,7 @@ toy_compiler_legalize_for_asm(struct toy_compiler *tc)
}
break;
case GEN6_OPCODE_IF:
if (tc->dev->gen >= ILO_GEN(7) &&
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7) &&
inst->cond_modifier != GEN6_COND_NONE) {
struct toy_inst *inst2;
@@ -590,7 +591,7 @@ toy_compiler_legalize_for_asm(struct toy_compiler *tc)
}
/* MRF to GRF */
if (tc->dev->gen >= ILO_GEN(7)) {
if (ilo_dev_gen(tc->dev) >= ILO_GEN(7)) {
for (i = 0; i < Elements(inst->src); i++) {
if (inst->src[i].file != TOY_FILE_MRF)
continue;