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anv: Port over CACHE_MODE_1 optimization fix enables from brw.

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Ben and I haven't observed these to help anything, but they enable
hardware optimizations for particular cases.  It's probably best to
enable them ahead of time, before we run into such a case.

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Kenneth Graunke
2017-05-23 21:33:12 -07:00
parent 53368b008e
commit 56535959fd
1 changed files with 13 additions and 0 deletions
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13
src/intel/vulkan/genX_state.c
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@@ -52,6 +52,19 @@ genX(init_device_state)(struct anv_device *device)
ps.PipelineSelection = _3D;
}
#if GEN_GEN >= 9
uint32_t cache_mode_1;
anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
.PartialResolveDisableInVC = true,
.PartialResolveDisableInVCMask = true,
.FloatBlendOptimizationEnable = true,
.FloatBlendOptimizationEnableMask = true);
anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
lri.RegisterOffset = GENX(CACHE_MODE_1_num);
lri.DataDWord = cache_mode_1;
}
#endif
anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa);
anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {