OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

i965: Do NIR shader cloning in the caller.

Browse Source 
This moves nir_shader_clone() to the driver-specific compile function,
rather than the shared src/intel/compiler code.  This allows i965 to do
key-specific passes before calling brw_compile_*.  Vulkan should not
need this cloning as it doesn't compile multiple variants.

We do need to continue cloning in the compute shader code because we
lower various things in NIR based on the SIMD width.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
This commit is contained in:
Kenneth Graunke
2018-11-08 22:10:03 -08:00
parent 6a10dd08f4
commit 562448b75a
12 changed files with 17 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/intel/compiler/brw_compiler.h
View File

@@ -1239,7 +1239,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_vs_prog_key *key,
struct brw_vs_prog_data *prog_data,
const struct nir_shader *shader,
struct nir_shader *shader,
int shader_time_index,
char **error_str);
@@ -1254,7 +1254,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
void *mem_ctx,
const struct brw_tcs_prog_key *key,
struct brw_tcs_prog_data *prog_data,
const struct nir_shader *nir,
struct nir_shader *nir,
int shader_time_index,
char **error_str);
@@ -1269,7 +1269,7 @@ brw_compile_tes(const struct brw_compiler *compiler, void *log_data,
const struct brw_tes_prog_key *key,
const struct brw_vue_map *input_vue_map,
struct brw_tes_prog_data *prog_data,
const struct nir_shader *shader,
struct nir_shader *shader,
struct gl_program *prog,
int shader_time_index,
char **error_str);
@@ -1284,7 +1284,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_gs_prog_key *key,
struct brw_gs_prog_data *prog_data,
const struct nir_shader *shader,
struct nir_shader *shader,
struct gl_program *prog,
int shader_time_index,
char **error_str);
@@ -1331,7 +1331,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_wm_prog_key *key,
struct brw_wm_prog_data *prog_data,
const struct nir_shader *shader,
struct nir_shader *shader,
struct gl_program *prog,
int shader_time_index8,
int shader_time_index16,

3
src/intel/compiler/brw_fs.cpp
View File

@@ -7119,7 +7119,7 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_wm_prog_key *key,
struct brw_wm_prog_data *prog_data,
const nir_shader *src_shader,
nir_shader *shader,
struct gl_program *prog,
int shader_time_index8, int shader_time_index16,
int shader_time_index32, bool allow_spilling,
@@ -7128,7 +7128,6 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
{
const struct gen_device_info *devinfo = compiler->devinfo;
nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
shader = brw_nir_apply_sampler_key(shader, compiler, &key->tex, true);
brw_nir_lower_fs_inputs(shader, devinfo, key);
brw_nir_lower_fs_outputs(shader);

3
src/intel/compiler/brw_shader.cpp
View File

@@ -1189,7 +1189,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
const struct brw_tes_prog_key *key,
const struct brw_vue_map *input_vue_map,
struct brw_tes_prog_data *prog_data,
const nir_shader *src_shader,
nir_shader *nir,
struct gl_program *prog,
int shader_time_index,
char **error_str)
@@ -1198,7 +1198,6 @@ brw_compile_tes(const struct brw_compiler *compiler,
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
const unsigned *assembly;
nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
nir->info.inputs_read = key->inputs_read;
nir->info.patch_inputs_read = key->patch_inputs_read;

3
src/intel/compiler/brw_vec4.cpp
View File

@@ -2828,12 +2828,11 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_vs_prog_key *key,
struct brw_vs_prog_data *prog_data,
const nir_shader *src_shader,
nir_shader *shader,
int shader_time_index,
char **error_str)
{
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_VERTEX];
nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
shader = brw_nir_apply_sampler_key(shader, compiler, &key->tex, is_scalar);
const unsigned *assembly = NULL;

3
src/intel/compiler/brw_vec4_gs_visitor.cpp
View File

@@ -615,7 +615,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_gs_prog_key *key,
struct brw_gs_prog_data *prog_data,
const nir_shader *src_shader,
nir_shader *shader,
struct gl_program *prog,
int shader_time_index,
char **error_str)
@@ -625,7 +625,6 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
c.key = *key;
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_GEOMETRY];
nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
/* The GLSL linker will have already matched up GS inputs and the outputs
* of prior stages. The driver does extend VS outputs in some cases, but

3
src/intel/compiler/brw_vec4_tcs.cpp
View File

@@ -378,7 +378,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
void *mem_ctx,
const struct brw_tcs_prog_key *key,
struct brw_tcs_prog_data *prog_data,
const nir_shader *src_shader,
nir_shader *nir,
int shader_time_index,
char **error_str)
{
@@ -387,7 +387,6 @@ brw_compile_tcs(const struct brw_compiler *compiler,
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL];
const unsigned *assembly;
nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
nir->info.outputs_written = key->outputs_written;
nir->info.patch_outputs_written = key->patch_outputs_written;

2
src/mesa/drivers/dri/i965/brw_cs.c
View File

@@ -58,7 +58,7 @@ brw_codegen_cs_prog(struct brw_context *brw,
struct brw_cs_prog_data prog_data;
bool start_busy = false;
double start_time = 0;
nir_shader *nir = cp->program.nir;
nir_shader *nir = nir_shader_clone(mem_ctx, cp->program.nir);
memset(&prog_data, 0, sizeof(prog_data));

2
src/mesa/drivers/dri/i965/brw_gs.c
View File

@@ -89,7 +89,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
void *mem_ctx = ralloc_context(NULL);
nir_shader *nir = gp->program.nir;
nir_shader *nir = nir_shader_clone(mem_ctx, gp->program.nir);
assign_gs_binding_table_offsets(devinfo, &gp->program, &prog_data);

2
src/mesa/drivers/dri/i965/brw_tcs.c
View File

@@ -84,7 +84,7 @@ brw_codegen_tcs_prog(struct brw_context *brw, struct brw_program *tcp,
void *mem_ctx = ralloc_context(NULL);
if (tcp) {
nir = tcp->program.nir;
nir = nir_shader_clone(mem_ctx, tcp->program.nir);
} else {
const nir_shader_compiler_options *options =
ctx->Const.ShaderCompilerOptions[MESA_SHADER_TESS_CTRL].NirOptions;

3
src/mesa/drivers/dri/i965/brw_tes.c
View File

@@ -70,7 +70,6 @@ brw_codegen_tes_prog(struct brw_context *brw,
const struct brw_compiler *compiler = brw->screen->compiler;
const struct gen_device_info *devinfo = &brw->screen->devinfo;
struct brw_stage_state *stage_state = &brw->tes.base;
nir_shader *nir = tep->program.nir;
struct brw_tes_prog_data prog_data;
bool start_busy = false;
double start_time = 0;
@@ -79,6 +78,8 @@ brw_codegen_tes_prog(struct brw_context *brw,
void *mem_ctx = ralloc_context(NULL);
nir_shader *nir = nir_shader_clone(mem_ctx, tep->program.nir);
brw_assign_common_binding_table_offsets(devinfo, &tep->program,
&prog_data.base.base, 0);

2
src/mesa/drivers/dri/i965/brw_vs.c
View File

@@ -174,7 +174,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
mem_ctx = ralloc_context(NULL);
nir_shader *nir = vp->program.nir;
nir_shader *nir = nir_shader_clone(mem_ctx, vp->program.nir);
brw_assign_common_binding_table_offsets(devinfo, &vp->program,
&prog_data.base.base, 0);

2
src/mesa/drivers/dri/i965/brw_wm.c
View File

@@ -139,7 +139,7 @@ brw_codegen_wm_prog(struct brw_context *brw,
bool start_busy = false;
double start_time = 0;
nir_shader *nir = fp->program.nir;
nir_shader *nir = nir_shader_clone(mem_ctx, fp->program.nir);
memset(&prog_data, 0, sizeof(prog_data));