From 56158bd0c0a2f11995fbdd0100749165686f93d2 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 30 Jan 2023 08:44:17 +0100 Subject: [PATCH] radv: adjust ACCUM tessellation fields on GFX11+ Based on RadeonSI/PAL. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/si_cmd_buffer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index fb5afd30f86..13e43352d45 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -511,8 +511,8 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) if (physical_device->rad_info.gfx_level >= GFX11) { /* ACCUM fields changed their meaning. */ radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION, - S_028B50_ACCUM_ISOLINE(255) | S_028B50_ACCUM_TRI(255) | - S_028B50_ACCUM_QUAD(255) | S_028B50_DONUT_SPLIT_GFX9(24) | + S_028B50_ACCUM_ISOLINE(128) | S_028B50_ACCUM_TRI(128) | + S_028B50_ACCUM_QUAD(128) | S_028B50_DONUT_SPLIT_GFX9(24) | S_028B50_TRAP_SPLIT(6)); } else if (physical_device->rad_info.gfx_level >= GFX9) { radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,