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radv: move gl_shader_stage from radv_binary to radv_shader_info

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This way, both radv_shader and radv_shader_binary, provide the stage.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22029>
This commit is contained in:
Daniel Schürmann
2023-03-17 00:49:44 +01:00
committed by Marge Bot
parent 2c8d101c71
commit 55caea6453
6 changed files with 27 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/amd/compiler/aco_interface.cpp
View File

@@ -252,9 +252,8 @@ aco_compile_shader(const struct aco_compiler_options* options,
if (program->collect_statistics)
stats_size = aco_num_statistics * sizeof(uint32_t);
(*build_binary)(binary, shaders[shader_count - 1]->info.stage, &config, llvm_ir.c_str(),
llvm_ir.size(), disasm.c_str(), disasm.size(), program->statistics, stats_size,
exec_size, code.data(), code.size());
(*build_binary)(binary, &config, llvm_ir.c_str(), llvm_ir.size(), disasm.c_str(), disasm.size(),
program->statistics, stats_size, exec_size, code.data(), code.size());
}
void
@@ -292,8 +291,8 @@ aco_compile_rt_prolog(const struct aco_compiler_options* options,
if (get_disasm)
disasm = get_disasm_string(program.get(), code, exec_size);
(*build_prolog)(binary, MESA_SHADER_COMPUTE, &config, NULL, 0, disasm.c_str(), disasm.size(),
program->statistics, 0, exec_size, code.data(), code.size());
(*build_prolog)(binary, &config, NULL, 0, disasm.c_str(), disasm.size(), program->statistics, 0,
exec_size, code.data(), code.size());
}
void

16
src/amd/compiler/aco_interface.h
View File

@@ -44,18 +44,10 @@ struct aco_compiler_statistic_info {
char desc[64];
};
typedef void (aco_callback)(void **priv_ptr,
gl_shader_stage stage,
const struct ac_shader_config *config,
const char *llvm_ir_str,
unsigned llvm_ir_size,
const char *disasm_str,
unsigned disasm_size,
uint32_t *statistics,
uint32_t stats_size,
uint32_t exec_size,
const uint32_t *code,
uint32_t code_dw);
typedef void(aco_callback)(void** priv_ptr, const struct ac_shader_config* config,
const char* llvm_ir_str, unsigned llvm_ir_size, const char* disasm_str,
unsigned disasm_size, uint32_t* statistics, uint32_t stats_size,
uint32_t exec_size, const uint32_t* code, uint32_t code_dw);
typedef void (aco_shader_part_callback)(void **priv_ptr,
uint32_t num_sgprs,

8
src/amd/vulkan/radv_nir_to_llvm.c
View File

@@ -899,7 +899,7 @@ radv_llvm_compile(LLVMModuleRef M, char **pelf_buffer, size_t *pelf_size,
static void
ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm, LLVMModuleRef llvm_module,
struct radv_shader_binary **rbinary, gl_shader_stage stage, const char *name,
struct radv_shader_binary **rbinary, const char *name,
const struct radv_nir_compiler_options *options)
{
char *elf_buffer = NULL;
@@ -935,7 +935,6 @@ ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm, LLVMModuleRef llvm_modu
memcpy(rbin->data + elf_size, llvm_ir_string, llvm_ir_size + 1);
rbin->base.type = RADV_BINARY_TYPE_RTLD;
rbin->base.stage = stage;
rbin->base.total_size = alloc_size;
rbin->elf_size = elf_size;
rbin->llvm_ir_size = llvm_ir_size;
@@ -958,9 +957,8 @@ radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
llvm_module = ac_translate_nir_to_llvm(ac_llvm, options, info, nir, nir_count, args);
ac_compile_llvm_module(ac_llvm, llvm_module, rbinary, nir[nir_count - 1]->info.stage,
radv_get_shader_name(info, nir[nir_count - 1]->info.stage),
options);
ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
radv_get_shader_name(info, nir[nir_count - 1]->info.stage), options);
}
void

30
src/amd/vulkan/radv_shader.c
View File

@@ -1831,14 +1831,14 @@ radv_open_rtld_binary(struct radv_device *device, const struct radv_shader_binar
unsigned num_lds_symbols = 0;
if (device->physical_device->rad_info.gfx_level >= GFX9 &&
(binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg)) {
(binary->info.stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg)) {
struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
sym->name = "esgs_ring";
sym->size = binary->info.ngg_info.esgs_ring_size;
sym->align = 64 * 1024;
}
if (binary->info.is_ngg && binary->stage == MESA_SHADER_GEOMETRY) {
if (binary->info.is_ngg && binary->info.stage == MESA_SHADER_GEOMETRY) {
struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
sym->name = "ngg_emit";
sym->size = binary->info.ngg_info.ngg_emit_size * 4;
@@ -1852,7 +1852,7 @@ radv_open_rtld_binary(struct radv_device *device, const struct radv_shader_binar
struct ac_rtld_open_info open_info = {
.info = &device->physical_device->rad_info,
.shader_type = binary->stage,
.shader_type = binary->info.stage,
.wave_size = binary->info.wave_size,
.num_parts = 1,
.elf_ptrs = &elf_data,
@@ -1890,7 +1890,7 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
unsigned encode_granularity = device->physical_device->rad_info.lds_encode_granularity;
config->lds_size = DIV_ROUND_UP(rtld_binary.lds_size, encode_granularity);
}
if (!config->lds_size && binary->stage == MESA_SHADER_TESS_CTRL) {
if (!config->lds_size && binary->info.stage == MESA_SHADER_TESS_CTRL) {
/* This is used for reporting LDS statistics */
config->lds_size = binary->info.tcs.num_lds_blocks;
}
@@ -1901,7 +1901,7 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
}
const struct radv_shader_info *info = &binary->info;
gl_shader_stage stage = binary->stage;
gl_shader_stage stage = binary->info.stage;
const struct radv_physical_device *pdevice = device->physical_device;
bool scratch_enabled = config->scratch_bytes_per_wave > 0 || info->cs.is_rt_shader;
bool trap_enabled = !!device->trap_handler_shader;
@@ -2541,18 +2541,10 @@ radv_dump_nir_shaders(struct nir_shader *const *shaders, int shader_count)
}
static void
radv_aco_build_shader_binary(void **bin,
gl_shader_stage stage,
const struct ac_shader_config *config,
const char *llvm_ir_str,
unsigned llvm_ir_size,
const char *disasm_str,
unsigned disasm_size,
uint32_t *statistics,
uint32_t stats_size,
uint32_t exec_size,
const uint32_t *code,
uint32_t code_dw)
radv_aco_build_shader_binary(void **bin, const struct ac_shader_config *config,
const char *llvm_ir_str, unsigned llvm_ir_size, const char *disasm_str,
unsigned disasm_size, uint32_t *statistics, uint32_t stats_size,
uint32_t exec_size, const uint32_t *code, uint32_t code_dw)
{
struct radv_shader_binary **binary = (struct radv_shader_binary **)bin;
size_t size = llvm_ir_size;
@@ -2568,7 +2560,6 @@ radv_aco_build_shader_binary(void **bin,
* from the start less than sizeof(radv_shader_binary_legacy). */
struct radv_shader_binary_legacy *legacy_binary = (struct radv_shader_binary_legacy *)calloc(size, 1);
legacy_binary->base.type = RADV_BINARY_TYPE_LEGACY;
legacy_binary->base.stage = stage;
legacy_binary->base.total_size = size;
legacy_binary->base.config = *config;
@@ -2829,6 +2820,7 @@ radv_create_rt_prolog(struct radv_device *device)
device->instance->debug_flags & RADV_DEBUG_DUMP_PROLOGS, false,
device->instance->debug_flags & RADV_DEBUG_HANG, false);
struct radv_shader_info info = {0};
info.stage = MESA_SHADER_COMPUTE;
info.loads_push_constants = true;
info.desc_set_used_mask = -1; /* just to force indirection */
info.wave_size = device->physical_device->rt_wave_size;
@@ -2898,6 +2890,7 @@ radv_create_vs_prolog(struct radv_device *device, const struct radv_vs_prolog_ke
device->instance->debug_flags & RADV_DEBUG_HANG, false);
struct radv_shader_info info = {0};
info.stage = MESA_SHADER_VERTEX;
info.wave_size = key->wave32 ? 32 : 64;
info.vs.needs_instance_id = true;
info.vs.needs_base_instance = true;
@@ -2964,6 +2957,7 @@ radv_create_ps_epilog(struct radv_device *device, const struct radv_ps_epilog_ke
device->instance->debug_flags & RADV_DEBUG_HANG, false);
struct radv_shader_info info = {0};
info.stage = MESA_SHADER_FRAGMENT;
info.wave_size = device->physical_device->ps_wave_size;
info.workgroup_size = 64;

3
src/amd/vulkan/radv_shader.h
View File

@@ -262,6 +262,8 @@ struct radv_shader_info {
struct radv_vs_output_info outinfo;
unsigned workgroup_size;
bool force_vrs_per_vertex;
gl_shader_stage stage;
struct {
uint8_t input_usage_mask[RADV_VERT_ATTRIB_MAX];
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
@@ -430,7 +432,6 @@ enum radv_shader_binary_type { RADV_BINARY_TYPE_LEGACY, RADV_BINARY_TYPE_RTLD };
struct radv_shader_binary {
enum radv_shader_binary_type type;
gl_shader_stage stage;
struct ac_shader_config config;
struct radv_shader_info info;

2
src/amd/vulkan/radv_shader_info.c
View File

@@ -742,6 +742,8 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
bool consider_force_vrs,
struct radv_shader_info *info)
{
info->stage = nir->info.stage;
struct nir_function *func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
if (layout && layout->dynamic_offset_count &&