gallium/radeon: fix warnings
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@@ -814,6 +814,8 @@ unsigned bc_finalizer::get_stack_depth(node *n, unsigned &loops,
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if (has_non_wqm_push)
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++stack_elements;
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break;
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case HW_CLASS_UNKNOWN:
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assert(0);
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}
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return stack_elements;
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}
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@@ -159,7 +159,7 @@ emit_fetch(
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struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
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struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
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LLVMBuilderRef builder = bld_base->base.gallivm->builder;
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LLVMValueRef result, ptr;
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LLVMValueRef result = NULL, ptr;
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if (swizzle == ~0) {
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LLVMValueRef values[TGSI_NUM_CHANNELS];
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@@ -409,8 +409,10 @@ emit_store(
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break;
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case TGSI_FILE_TEMPORARY:
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if (uses_temp_indirect_addressing(bld_base))
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if (uses_temp_indirect_addressing(bld_base)) {
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temp_ptr = NULL;
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break;
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}
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temp_ptr = ctx->temps[ TGSI_NUM_CHANNELS * reg->Register.Index + chan_index];
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break;
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@@ -101,7 +101,7 @@ void radeon_dump_cs_on_lockup(struct radeon_drm_cs *cs, struct radeon_cs_context
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for (j = 0; j < ndw; j++) {
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if (j && !(j % 8)) {
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uint32_t offset = (j - 8) << 2;
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fprintf(dump, " /* [0x%08x] va[0x%016lx] */\n ", offset, offset + csc->relocs_bo[i]->va);
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fprintf(dump, " /* [0x%08x] va[0x%016llx] */\n ", offset, offset + csc->relocs_bo[i]->va);
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}
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fprintf(dump, " 0x%08x,", ptr[j]);
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}
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@@ -143,10 +143,10 @@ void radeon_dump_cs_on_lockup(struct radeon_drm_cs *cs, struct radeon_cs_context
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ptr = radeon_bo_do_map(csc->relocs_bo[i]);
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if (ptr) {
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fprintf(dump, " bo[%d] = bo_new(&ctx, %d, bo_%04d_data, 0x%016lx, 0x%08x);\n",
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fprintf(dump, " bo[%d] = bo_new(&ctx, %d, bo_%04d_data, 0x%016llx, 0x%08x);\n",
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i, ndw, i, csc->relocs_bo[i]->va, csc->relocs_bo[i]->base.alignment);
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} else {
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fprintf(dump, " bo[%d] = bo_new(&ctx, %d, NULL, 0x%016lx, 0x%08x);\n",
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fprintf(dump, " bo[%d] = bo_new(&ctx, %d, NULL, 0x%016llx, 0x%08x);\n",
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i, ndw, csc->relocs_bo[i]->va, csc->relocs_bo[i]->base.alignment);
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}
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}
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