intel: Start adding defines and some bits for sandybridge bringup.

src/mesa/drivers/dri/i965/brw_draw.c

@@ -124,6 +124,10 @@ static void brw_emit_prim(struct brw_context *brw,
    struct brw_3d_primitive prim_packet;
    struct intel_context *intel = &brw->intel;
 
+   /* Last thing to hook up in the pipeline when brw_state_upload.c is done. */
+   if (IS_GEN6(intel->intelScreen->deviceID))
+      return;
+
    if (INTEL_DEBUG & DEBUG_PRIMS)
       printf("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim->mode), 
 		   prim->start, prim->count);

src/mesa/drivers/dri/i965/brw_state_upload.c

@@ -35,8 +35,15 @@
 #include "brw_state.h"
 #include "intel_batchbuffer.h"
 #include "intel_buffers.h"
+#include "intel_chipset.h"
 
-static const struct brw_tracked_state *atoms[] =
+/* This is used to initialize brw->state.atoms[].  We could use this
+ * list directly except for a single atom, brw_constant_buffer, which
+ * has a .dirty value which changes according to the parameters of the
+ * current fragment and vertex programs, and so cannot be a static
+ * value.
+ */
+static const struct brw_tracked_state *gen4_atoms[] =
 {
    &brw_check_fallback,
 
@@ -95,6 +102,66 @@ static const struct brw_tracked_state *atoms[] =
    &brw_constant_buffer
 };
 
+const struct brw_tracked_state *gen6_atoms[] =
+{
+   &brw_check_fallback,
+
+#if 0
+   &brw_wm_input_sizes,
+   &brw_vs_prog,
+   &brw_gs_prog,
+   &brw_clip_prog,
+   &brw_sf_prog,
+   &brw_wm_prog,
+
+   /* Once all the programs are done, we know how large urb entry
+    * sizes need to be and can decide if we need to change the urb
+    * layout.
+    */
+   &brw_curbe_offsets,
+   &brw_recalculate_urb_fence,
+
+   &brw_cc_vp,
+   &brw_cc_unit,
+
+   &brw_vs_surfaces,		/* must do before unit */
+   &brw_wm_constant_surface,	/* must do before wm surfaces/bind bo */
+   &brw_wm_surfaces,		/* must do before samplers and unit */
+   &brw_wm_samplers,
+
+   &brw_wm_unit,
+   &brw_sf_vp,
+   &brw_sf_unit,
+   &brw_vs_unit,		/* always required, enabled or not */
+   &brw_clip_unit,
+   &brw_gs_unit,
+
+   /* Command packets:
+    */
+   &brw_invarient_state,
+   &brw_state_base_address,
+
+   &brw_binding_table_pointers,
+   &brw_blend_constant_color,
+
+   &brw_depthbuffer,
+
+   &brw_polygon_stipple,
+   &brw_polygon_stipple_offset,
+
+   &brw_line_stipple,
+   &brw_aa_line_parameters,
+
+   &brw_psp_urb_cbs,
+
+   &brw_drawing_rect,
+   &brw_indices,
+   &brw_index_buffer,
+   &brw_vertices,
+
+   &brw_constant_buffer
+#endif
+};
 
 void brw_init_state( struct brw_context *brw )
 {
@@ -270,6 +337,8 @@ void brw_validate_state( struct brw_context *brw )
    struct intel_context *intel = &brw->intel;
    struct brw_state_flags *state = &brw->state.dirty;
    GLuint i;
+   const struct brw_tracked_state **atoms;
+   int num_atoms;
 
    brw_clear_validated_bos(brw);
 
@@ -278,6 +347,14 @@ void brw_validate_state( struct brw_context *brw )
 
    brw_add_validated_bo(brw, intel->batch->buf);
 
+   if (IS_GEN6(intel->intelScreen->deviceID)) {
+      atoms = gen6_atoms;
+      num_atoms = ARRAY_SIZE(gen6_atoms);
+   } else {
+      atoms = gen4_atoms;
+      num_atoms = ARRAY_SIZE(gen4_atoms);
+   }
+
    if (brw->emit_state_always) {
       state->mesa |= ~0;
       state->brw |= ~0;
@@ -305,7 +382,7 @@ void brw_validate_state( struct brw_context *brw )
    brw->intel.Fallback = GL_FALSE; /* boolean, not bitfield */
 
    /* do prepare stage for all atoms */
-   for (i = 0; i < Elements(atoms); i++) {
+   for (i = 0; i < num_atoms; i++) {
       const struct brw_tracked_state *atom = atoms[i];
 
       if (brw->intel.Fallback)
@@ -337,9 +414,20 @@ void brw_validate_state( struct brw_context *brw )
 
 void brw_upload_state(struct brw_context *brw)
 {
+   struct intel_context *intel = &brw->intel;
    struct brw_state_flags *state = &brw->state.dirty;
    int i;
    static int dirty_count = 0;
+   const struct brw_tracked_state **atoms;
+   int num_atoms;
+
+   if (IS_GEN6(intel->intelScreen->deviceID)) {
+      atoms = gen6_atoms;
+      num_atoms = ARRAY_SIZE(gen6_atoms);
+   } else {
+      atoms = gen4_atoms;
+      num_atoms = ARRAY_SIZE(gen4_atoms);
+   }
 
    brw_clear_validated_bos(brw);
 
@@ -352,7 +440,7 @@ void brw_upload_state(struct brw_context *brw)
       memset(&examined, 0, sizeof(examined));
       prev = *state;
 
-      for (i = 0; i < Elements(atoms); i++) {	 
+      for (i = 0; i < num_atoms; i++) {
 	 const struct brw_tracked_state *atom = atoms[i];
 	 struct brw_state_flags generated;
 
@@ -381,7 +469,7 @@ void brw_upload_state(struct brw_context *brw)
       }
    }
    else {
-      for (i = 0; i < Elements(atoms); i++) {	 
+      for (i = 0; i < num_atoms; i++) {
 	 const struct brw_tracked_state *atom = atoms[i];
 
 	 if (brw->intel.Fallback)

src/mesa/drivers/dri/intel/intel_blit.c

@@ -89,6 +89,10 @@ intelEmitCopyBlit(struct intel_context *intel,
    dri_bo *aper_array[3];
    BATCH_LOCALS;
 
+   /* Blits are in a different ringbuffer so we don't use them. */
+   if (intel->gen >= 6)
+      return GL_FALSE;
+
    if (dst_tiling != I915_TILING_NONE) {
       if (dst_offset & 4095)
 	 return GL_FALSE;
@@ -218,6 +222,9 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
    GLint cx, cy, cw, ch;
    BATCH_LOCALS;
 
+   /* Blits are in a different ringbuffer so we don't use them. */
+   assert(intel->gen < 6);
+
    /*
     * Compute values for clearing the buffers.
     */
@@ -388,6 +395,10 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
    int dwords = ALIGN(src_size, 8) / 4;
    uint32_t opcode, br13, blit_cmd;
 
+   /* Blits are in a different ringbuffer so we don't use them. */
+   if (intel->gen >= 6)
+      return GL_FALSE;
+
    if (dst_tiling != I915_TILING_NONE) {
       if (dst_offset & 4095)
 	 return GL_FALSE;
@@ -473,6 +484,9 @@ intel_emit_linear_blit(struct intel_context *intel,
 {
    GLuint pitch, height;
 
+   /* Blits are in a different ringbuffer so we don't use them. */
+   assert(intel->gen < 6);
+
    /* The pitch is a signed value. */
    pitch = MIN2(size, (1 << 15) - 1);
    height = size / pitch;

src/mesa/drivers/dri/intel/intel_chipset.h

@@ -1,4 +1,4 @@
-/*
+ /*
  * Copyright © 2007 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -71,6 +71,8 @@
 #define PCI_CHIP_ILD_G                  0x0042
 #define PCI_CHIP_ILM_G                  0x0046
 
+#define PCI_CHIP_SANDYBRIDGE		0x0102
+
 #define IS_MOBILE(devid)	(devid == PCI_CHIP_I855_GM || \
 				 devid == PCI_CHIP_I915_GM || \
 				 devid == PCI_CHIP_I945_GM || \
@@ -104,14 +106,20 @@
 				 devid == PCI_CHIP_Q33_G || \
 				 devid == PCI_CHIP_Q35_G || IS_IGD(devid))
 
-#define IS_965(devid)		(devid == PCI_CHIP_I965_G || \
+#define IS_GEN4(devid)		(devid == PCI_CHIP_I965_G || \
 				 devid == PCI_CHIP_I965_Q || \
 				 devid == PCI_CHIP_I965_G_1 || \
 				 devid == PCI_CHIP_I965_GM || \
 				 devid == PCI_CHIP_I965_GME || \
 				 devid == PCI_CHIP_I946_GZ || \
+				 IS_G4X(devid))
+
+#define IS_GEN6(devid)		(devid == PCI_CHIP_SANDYBRIDGE)
+
+#define IS_965(devid)		(IS_GEN4(devid) || \
 				 IS_G4X(devid) || \
-				 IS_IGDNG(devid))
+				 IS_IGDNG(devid) || \
+				 IS_GEN6(devid))
 
 #define IS_9XX(devid)		(IS_915(devid) || \
 				 IS_945(devid) || \

src/mesa/drivers/dri/intel/intel_clear.c

@@ -133,6 +133,12 @@ intelClear(GLcontext *ctx, GLbitfield mask)
       }
    }
 
+   if (intel->gen >= 6) {
+      /* Blits are in a different ringbuffer so we don't use them. */
+      tri_mask |= blit_mask;
+      blit_mask = 0;
+   }
+
    /* SW fallback clearing */
    swrast_mask = mask & ~tri_mask & ~blit_mask;
 

src/mesa/drivers/dri/intel/intel_context.c

@@ -610,7 +610,9 @@ intelInitContext(struct intel_context *intel,
    intel->driContext = driContextPriv;
    intel->driFd = sPriv->fd;
 
-   if (IS_965(intel->intelScreen->deviceID)) {
+   if (IS_GEN6(intel->intelScreen->deviceID)) {
+      intel->gen = 6;
+   } else if (IS_965(intel->intelScreen->deviceID)) {
       intel->gen = 4;
    } else if (IS_9XX(intel->intelScreen->deviceID)) {
       intel->gen = 3;