etnaviv: hide TS sharing behind debug option

TS sharing isn't fully stable yet. There are some fixes pending, but they
don't take care of all reported issues. Hide TS sharing behind a debug
switch until all the known issues are resolved.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20606>
This commit is contained in:
Lucas Stach
2023-01-10 12:11:35 +01:00
committed by Marge Bot
parent 9572ecbee9
commit 54f583738e
3 changed files with 6 additions and 2 deletions

View File

@@ -56,6 +56,7 @@
#define ETNA_DBG_NOCACHE 0x1000000 /* Disable shader cache */
#define ETNA_DBG_LINEAR_PE 0x2000000 /* Enable linear PE */
#define ETNA_DBG_MSAA 0x4000000 /* Enable MSAA */
#define ETNA_DBG_SHARED_TS 0x8000000 /* Enable TS sharing */
extern int etna_mesa_debug; /* set in etnaviv_screen.c from ETNA_MESA_DEBUG */

View File

@@ -519,7 +519,8 @@ select_best_modifier(const struct etna_screen * screen,
best_modifier = base_modifier = priority_to_modifier[prio];
if (!VIV_FEATURE(screen, chipFeatures, FAST_CLEAR))
if (!DBG_ENABLED(ETNA_DBG_SHARED_TS) ||
!VIV_FEATURE(screen, chipFeatures, FAST_CLEAR))
return best_modifier;
/* Make a second pass to try and find the best TS modifier if any. */

View File

@@ -74,6 +74,7 @@ static const struct debug_named_value etna_debug_options[] = {
{"nocache", ETNA_DBG_NOCACHE, "Disable shader cache"},
{"linear_pe", ETNA_DBG_LINEAR_PE, "Enable linear PE"},
{"msaa", ETNA_DBG_MSAA, "Enable MSAA support"},
{"shared_ts", ETNA_DBG_SHARED_TS, "Enable TS sharing"},
DEBUG_NAMED_VALUE_END
};
@@ -653,7 +654,8 @@ etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
int mods_multiplier = 1;
int i, j;
if (VIV_FEATURE(screen, chipFeatures, FAST_CLEAR)) {
if (DBG_ENABLED(ETNA_DBG_SHARED_TS) &&
VIV_FEATURE(screen, chipFeatures, FAST_CLEAR)) {
/* If TS is supported expose the TS modifiers. GPUs with feature
* CACHE128B256BPERLINE have both 128B and 256B color tile TS modes,
* older cores support exactly one TS layout.