radv: fix setting VGT_REUSE_OFF for TES on GFX10
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
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@@ -3338,6 +3338,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
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const struct radv_ngg_state *ngg_state)
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const struct radv_ngg_state *ngg_state)
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{
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{
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uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
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uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
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gl_shader_stage es_type =
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radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
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radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
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radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
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radeon_emit(cs, va >> 8);
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radeon_emit(cs, va >> 8);
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@@ -3388,9 +3390,12 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
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cull_dist_mask << 8 |
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cull_dist_mask << 8 |
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clip_dist_mask);
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clip_dist_mask);
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/* TODO: Correctly set REUSE_OFF */
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bool vgt_reuse_off = pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 &&
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pipeline->device->physical_device->rad_info.chip_external_rev == 0x1 &&
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es_type == MESA_SHADER_TESS_EVAL;
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radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
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radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
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S_028AB4_REUSE_OFF(0));
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S_028AB4_REUSE_OFF(vgt_reuse_off));
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radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
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radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
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ngg_state->vgt_esgs_ring_itemsize);
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ngg_state->vgt_esgs_ring_itemsize);
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