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pvr: switch pvr_cmd_buffer_alloc_mem to use pvr_bo_suballoc

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Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22940>
This commit is contained in:
Luigi Santivetti
2023-05-10 08:29:41 +01:00
parent 42d1011216
commit 547a10f870
7 changed files with 129 additions and 130 deletions
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26
src/imagination/vulkan/pvr_blit.c
View File

@@ -1362,10 +1362,10 @@ static VkResult pvr_clear_color_attachment_static_create_consts_buffer(
const uint32_t clear_color[static const PVR_CLEAR_COLOR_ARRAY_SIZE],
ASSERTED bool uses_tile_buffer,
uint32_t tile_buffer_idx,
struct pvr_bo **const const_shareds_buffer_out)
struct pvr_suballoc_bo **const const_shareds_buffer_out)
{
struct pvr_device *device = cmd_buffer->device;
struct pvr_bo *const_shareds_buffer;
struct pvr_suballoc_bo *const_shareds_buffer;
struct pvr_bo *tile_buffer;
uint64_t tile_dev_addr;
uint32_t *buffer;
@@ -1382,7 +1382,7 @@ static VkResult pvr_clear_color_attachment_static_create_consts_buffer(
if (result != VK_SUCCESS)
return result;
buffer = const_shareds_buffer->bo->map;
buffer = pvr_bo_suballoc_get_map_addr(const_shareds_buffer);
for (uint32_t i = 0; i < PVR_CLEAR_ATTACHMENT_CONST_COUNT; i++) {
uint32_t dest_idx = shader_info->driver_const_location_map[i];
@@ -1428,8 +1428,6 @@ static VkResult pvr_clear_color_attachment_static_create_consts_buffer(
buffer[static_buff->dst_idx] = static_buff->value;
}
pvr_bo_cpu_unmap(device, const_shareds_buffer);
*const_shareds_buffer_out = const_shareds_buffer;
return VK_SUCCESS;
@@ -1456,9 +1454,9 @@ static VkResult pvr_clear_color_attachment_static(
struct pvr_pds_pixel_shader_sa_program texture_program;
uint32_t pds_state[PVR_STATIC_CLEAR_PDS_STATE_COUNT];
const struct pvr_shader_factory_info *shader_info;
struct pvr_suballoc_bo *pds_texture_program_bo;
struct pvr_static_clear_ppp_template template;
struct pvr_bo *pds_texture_program_bo;
struct pvr_bo *const_shareds_buffer;
struct pvr_suballoc_bo *const_shareds_buffer;
uint64_t pds_texture_program_addr;
uint32_t tile_buffer_idx = 0;
uint32_t out_reg_count;
@@ -1500,7 +1498,7 @@ static VkResult pvr_clear_color_attachment_static(
texture_program = (struct pvr_pds_pixel_shader_sa_program){
.num_texture_dma_kicks = 1,
.texture_dma_address = {
[0] = const_shareds_buffer->vma->dev_addr.addr,
[0] = const_shareds_buffer->dev_addr.addr,
}
};
/* clang-format on */
@@ -1526,13 +1524,13 @@ static VkResult pvr_clear_color_attachment_static(
&pds_texture_program_bo);
if (result != VK_SUCCESS) {
list_del(&const_shareds_buffer->link);
pvr_bo_free(device, const_shareds_buffer);
pvr_bo_suballoc_free(const_shareds_buffer);
return result;
}
buffer = pds_texture_program_bo->bo->map;
pds_texture_program_addr = pds_texture_program_bo->vma->dev_addr.addr -
buffer = pvr_bo_suballoc_get_map_addr(pds_texture_program_bo);
pds_texture_program_addr = pds_texture_program_bo->dev_addr.addr -
device->heaps.pds_heap->base_addr.addr;
pvr_pds_generate_pixel_shader_sa_texture_state_data(
@@ -1540,8 +1538,6 @@ static VkResult pvr_clear_color_attachment_static(
buffer,
&device->pdevice->dev_info);
pvr_bo_cpu_unmap(device, pds_texture_program_bo);
pvr_csb_pack (&pds_state[PVR_STATIC_CLEAR_PPP_PDS_TYPE_SHADERBASE],
TA_STATE_PDS_SHADERBASE,
shaderbase) {
@@ -1607,10 +1603,10 @@ static VkResult pvr_clear_color_attachment_static(
&pvr_bo);
if (result != VK_SUCCESS) {
list_del(&pds_texture_program_bo->link);
pvr_bo_free(device, pds_texture_program_bo);
pvr_bo_suballoc_free(pds_texture_program_bo);
list_del(&const_shareds_buffer->link);
pvr_bo_free(device, const_shareds_buffer);
pvr_bo_suballoc_free(const_shareds_buffer);
cmd_buffer->state.status = result;
return result;

5
src/imagination/vulkan/pvr_bo.c
View File

@@ -581,8 +581,9 @@ VkResult pvr_bo_suballoc(struct pvr_suballocator *allocator,
if (!suballoc_bo)
return vk_error(allocator->device, VK_ERROR_OUT_OF_HOST_MEMORY);
/* This cache line value is used for all type of allocations (i.e. USC, PDS
* and general), so always align them to at least the size of the cache line.
/* This cache line value is used for all type of allocations (i.e. USC, PDS,
* transfer and general), so always align them to at least the size of the
* cache line.
*/
align = MAX2(align, cache_line_size);
assert(util_is_power_of_two_nonzero(align));

124
src/imagination/vulkan/pvr_cmd_buffer.c
View File

@@ -2100,27 +2100,38 @@ VkResult pvr_cmd_buffer_alloc_mem(struct pvr_cmd_buffer *cmd_buffer,
struct pvr_winsys_heap *heap,
uint64_t size,
uint32_t flags,
struct pvr_bo **const pvr_bo_out)
struct pvr_suballoc_bo **const pvr_bo_out)
{
const uint32_t cache_line_size =
rogue_get_slc_cache_line_size(&cmd_buffer->device->pdevice->dev_info);
struct pvr_bo *pvr_bo;
struct pvr_suballoc_bo *suballoc_bo;
struct pvr_suballocator *allocator;
VkResult result;
result = pvr_bo_alloc(cmd_buffer->device,
heap,
size,
cache_line_size,
flags,
&pvr_bo);
/* We assume users to always request bo(s) to be CPU mapped */
assert(flags & PVR_BO_ALLOC_FLAG_CPU_MAPPED);
if (heap == cmd_buffer->device->heaps.general_heap)
allocator = &cmd_buffer->device->suballoc_general;
else if (heap == cmd_buffer->device->heaps.pds_heap)
allocator = &cmd_buffer->device->suballoc_pds;
else if (heap == cmd_buffer->device->heaps.transfer_3d_heap)
allocator = &cmd_buffer->device->suballoc_transfer;
else if (heap == cmd_buffer->device->heaps.usc_heap)
allocator = &cmd_buffer->device->suballoc_usc;
else
unreachable("Unknown heap type");
result =
pvr_bo_suballoc(allocator, size, cache_line_size, false, &suballoc_bo);
if (result != VK_SUCCESS) {
cmd_buffer->state.status = result;
return result;
}
list_add(&pvr_bo->link, &cmd_buffer->bo_list);
list_add(&suballoc_bo->link, &cmd_buffer->bo_list);
*pvr_bo_out = pvr_bo;
*pvr_bo_out = suballoc_bo;
return VK_SUCCESS;
}
@@ -2996,10 +3007,10 @@ pvr_setup_vertex_buffers(struct pvr_cmd_buffer *cmd_buffer,
&gfx_pipeline->shader_state.vertex;
struct pvr_cmd_buffer_state *const state = &cmd_buffer->state;
const struct pvr_pds_info *const pds_info = state->pds_shader.info;
struct pvr_suballoc_bo *pvr_bo;
const uint8_t *entries;
uint32_t *dword_buffer;
uint64_t *qword_buffer;
struct pvr_bo *pvr_bo;
VkResult result;
result =
@@ -3011,8 +3022,8 @@ pvr_setup_vertex_buffers(struct pvr_cmd_buffer *cmd_buffer,
if (result != VK_SUCCESS)
return result;
dword_buffer = (uint32_t *)pvr_bo->bo->map;
qword_buffer = (uint64_t *)pvr_bo->bo->map;
dword_buffer = (uint32_t *)pvr_bo_suballoc_get_map_addr(pvr_bo);
qword_buffer = (uint64_t *)pvr_bo_suballoc_get_map_addr(pvr_bo);
entries = (uint8_t *)pds_info->entries;
@@ -3187,11 +3198,9 @@ pvr_setup_vertex_buffers(struct pvr_cmd_buffer *cmd_buffer,
}
state->pds_vertex_attrib_offset =
pvr_bo->vma->dev_addr.addr -
pvr_bo->dev_addr.addr -
cmd_buffer->device->heaps.pds_heap->base_addr.addr;
pvr_bo_cpu_unmap(cmd_buffer->device, pvr_bo);
return VK_SUCCESS;
}
@@ -3204,10 +3213,10 @@ static VkResult pvr_setup_descriptor_mappings_old(
{
const struct pvr_pds_info *const pds_info = &descriptor_state->pds_info;
const struct pvr_descriptor_state *desc_state;
struct pvr_suballoc_bo *pvr_bo;
const uint8_t *entries;
uint32_t *dword_buffer;
uint64_t *qword_buffer;
struct pvr_bo *pvr_bo;
VkResult result;
if (!pds_info->data_size_in_dwords)
@@ -3222,8 +3231,8 @@ static VkResult pvr_setup_descriptor_mappings_old(
if (result != VK_SUCCESS)
return result;
dword_buffer = (uint32_t *)pvr_bo->bo->map;
qword_buffer = (uint64_t *)pvr_bo->bo->map;
dword_buffer = (uint32_t *)pvr_bo_suballoc_get_map_addr(pvr_bo);
qword_buffer = (uint64_t *)pvr_bo_suballoc_get_map_addr(pvr_bo);
entries = (uint8_t *)pds_info->entries;
@@ -3425,10 +3434,8 @@ static VkResult pvr_setup_descriptor_mappings_old(
}
}
pvr_bo_cpu_unmap(cmd_buffer->device, pvr_bo);
*descriptor_data_offset_out =
pvr_bo->vma->dev_addr.addr -
pvr_bo->dev_addr.addr -
cmd_buffer->device->heaps.pds_heap->base_addr.addr;
return VK_SUCCESS;
@@ -3509,7 +3516,7 @@ static VkResult pvr_cmd_buffer_upload_patched_desc_set(
struct pvr_cmd_buffer *cmd_buffer,
const struct pvr_descriptor_set *desc_set,
const uint32_t *dynamic_offsets,
struct pvr_bo **const bo_out)
struct pvr_suballoc_bo **const bo_out)
{
const struct pvr_descriptor_set_layout *layout = desc_set->layout;
const uint64_t normal_desc_set_size =
@@ -3519,8 +3526,8 @@ static VkResult pvr_cmd_buffer_upload_patched_desc_set(
struct pvr_descriptor_size_info dynamic_uniform_buffer_size_info;
struct pvr_descriptor_size_info dynamic_storage_buffer_size_info;
struct pvr_device *device = cmd_buffer->device;
struct pvr_bo *patched_desc_set_bo;
uint32_t *mem_ptr;
struct pvr_suballoc_bo *patched_desc_set_bo;
uint32_t *src_mem_ptr, *dst_mem_ptr;
VkResult result;
assert(desc_set->layout->dynamic_buffer_count > 0);
@@ -3547,9 +3554,10 @@ static VkResult pvr_cmd_buffer_upload_patched_desc_set(
if (result != VK_SUCCESS)
return result;
mem_ptr = (uint32_t *)patched_desc_set_bo->bo->map;
src_mem_ptr = (uint32_t *)desc_set->pvr_bo->bo->map;
dst_mem_ptr = (uint32_t *)pvr_bo_suballoc_get_map_addr(patched_desc_set_bo);
memcpy(mem_ptr, desc_set->pvr_bo->bo->map, normal_desc_set_size);
memcpy(dst_mem_ptr, src_mem_ptr, normal_desc_set_size);
for (uint32_t i = 0; i < desc_set->layout->binding_count; i++) {
const struct pvr_descriptor_set_layout_binding *binding =
@@ -3629,18 +3637,17 @@ static VkResult pvr_cmd_buffer_upload_patched_desc_set(
assert(descriptors[desc_idx].type == binding->type);
memcpy(mem_ptr + primary_offset + size_info->primary * desc_idx,
memcpy(dst_mem_ptr + primary_offset + size_info->primary * desc_idx,
&addr.addr,
PVR_DW_TO_BYTES(size_info->primary));
memcpy(mem_ptr + secondary_offset + size_info->secondary * desc_idx,
memcpy(dst_mem_ptr + secondary_offset +
size_info->secondary * desc_idx,
&range,
PVR_DW_TO_BYTES(size_info->secondary));
}
}
}
pvr_bo_cpu_unmap(device, patched_desc_set_bo);
*bo_out = patched_desc_set_bo;
return VK_SUCCESS;
@@ -3702,7 +3709,7 @@ pvr_cmd_buffer_upload_desc_set_table(struct pvr_cmd_buffer *const cmd_buffer,
desc_set = desc_state->descriptor_sets[set];
if (desc_set->layout->dynamic_buffer_count > 0) {
struct pvr_bo *new_desc_set_bo;
struct pvr_suballoc_bo *new_desc_set_bo;
assert(dynamic_offset_idx + desc_set->layout->dynamic_buffer_count <=
ARRAY_SIZE(desc_state->dynamic_offsets));
@@ -3717,7 +3724,7 @@ pvr_cmd_buffer_upload_desc_set_table(struct pvr_cmd_buffer *const cmd_buffer,
dynamic_offset_idx += desc_set->layout->dynamic_buffer_count;
bound_desc_sets[set] = new_desc_set_bo->vma->dev_addr.addr;
bound_desc_sets[set] = new_desc_set_bo->dev_addr.addr;
} else {
bound_desc_sets[set] = desc_set->pvr_bo->vma->dev_addr.addr;
}
@@ -3806,10 +3813,10 @@ static VkResult pvr_setup_descriptor_mappings_new(
uint32_t *const descriptor_data_offset_out)
{
const struct pvr_pds_info *const pds_info = &descriptor_state->pds_info;
struct pvr_suballoc_bo *pvr_bo;
const uint8_t *entries;
uint32_t *dword_buffer;
uint64_t *qword_buffer;
struct pvr_bo *pvr_bo;
VkResult result;
if (!pds_info->data_size_in_dwords)
@@ -3823,8 +3830,8 @@ static VkResult pvr_setup_descriptor_mappings_new(
if (result != VK_SUCCESS)
return result;
dword_buffer = (uint32_t *)pvr_bo->bo->map;
qword_buffer = (uint64_t *)pvr_bo->bo->map;
dword_buffer = (uint32_t *)pvr_bo_suballoc_get_map_addr(pvr_bo);
qword_buffer = (uint64_t *)pvr_bo_suballoc_get_map_addr(pvr_bo);
entries = (uint8_t *)pds_info->entries;
@@ -3862,7 +3869,7 @@ static VkResult pvr_setup_descriptor_mappings_new(
*const addr_literal_buffer_entry =
(struct pvr_pds_const_map_entry_addr_literal_buffer *)entries;
struct pvr_device *device = cmd_buffer->device;
struct pvr_bo *addr_literal_buffer_bo;
struct pvr_suballoc_bo *addr_literal_buffer_bo;
uint32_t addr_literal_count = 0;
uint64_t *addr_literal_buffer;
@@ -3874,12 +3881,13 @@ static VkResult pvr_setup_descriptor_mappings_new(
if (result != VK_SUCCESS)
return result;
addr_literal_buffer = (uint64_t *)addr_literal_buffer_bo->bo->map;
addr_literal_buffer =
(uint64_t *)pvr_bo_suballoc_get_map_addr(addr_literal_buffer_bo);
entries += sizeof(*addr_literal_buffer_entry);
PVR_WRITE(qword_buffer,
addr_literal_buffer_bo->vma->dev_addr.addr,
addr_literal_buffer_bo->dev_addr.addr,
addr_literal_buffer_entry->const_offset,
pds_info->data_size_in_dwords);
@@ -3912,7 +3920,6 @@ static VkResult pvr_setup_descriptor_mappings_new(
i += addr_literal_count;
pvr_bo_cpu_unmap(device, addr_literal_buffer_bo);
break;
}
@@ -3921,10 +3928,8 @@ static VkResult pvr_setup_descriptor_mappings_new(
}
}
pvr_bo_cpu_unmap(cmd_buffer->device, pvr_bo);
*descriptor_data_offset_out =
pvr_bo->vma->dev_addr.addr -
pvr_bo->dev_addr.addr -
cmd_buffer->device->heaps.pds_heap->base_addr.addr;
return VK_SUCCESS;
@@ -5315,7 +5320,7 @@ static VkResult pvr_emit_ppp_state(struct pvr_cmd_buffer *const cmd_buffer,
uint32_t *buffer_ptr = ppp_state_words;
uint32_t dbsc_patching_offset = 0;
uint32_t ppp_state_words_count;
struct pvr_bo *pvr_bo;
struct pvr_suballoc_bo *pvr_bo;
VkResult result;
#if !defined(NDEBUG)
@@ -5536,18 +5541,18 @@ static VkResult pvr_emit_ppp_state(struct pvr_cmd_buffer *const cmd_buffer,
if (result != VK_SUCCESS)
return result;
memcpy(pvr_bo->bo->map,
memcpy(pvr_bo_suballoc_get_map_addr(pvr_bo),
ppp_state_words,
PVR_DW_TO_BYTES(ppp_state_words_count));
/* Write the VDM state update into the VDM control stream. */
pvr_csb_emit (control_stream, VDMCTRL_PPP_STATE0, state0) {
state0.word_count = ppp_state_words_count;
state0.addrmsb = pvr_bo->vma->dev_addr;
state0.addrmsb = pvr_bo->dev_addr;
}
pvr_csb_emit (control_stream, VDMCTRL_PPP_STATE1, state1) {
state1.addrlsb = pvr_bo->vma->dev_addr;
state1.addrlsb = pvr_bo->dev_addr;
}
if (emit_dbsc && cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) {
@@ -6160,9 +6165,9 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
const struct pvr_device_info *dev_info =
&cmd_buffer->device->pdevice->dev_info;
struct pvr_cmd_buffer_state *state = &cmd_buffer->state;
struct pvr_bo *dummy_bo;
struct pvr_suballoc_bo *dummy_bo;
struct pvr_suballoc_bo *pds_bo;
uint32_t *dummy_stream;
struct pvr_bo *pds_bo;
uint32_t *pds_base;
uint32_t pds_size;
VkResult result;
@@ -6192,7 +6197,7 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
if (result != VK_SUCCESS)
return result;
pds_base = pds_bo->bo->map;
pds_base = pvr_bo_suballoc_get_map_addr(pds_bo);
memcpy(pds_base,
pds_prog.program.code,
PVR_DW_TO_BYTES(pds_prog.program.code_size_aligned));
@@ -6211,8 +6216,6 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
dev_info);
}
pvr_bo_cpu_unmap(cmd_buffer->device, pds_bo);
/* Write the VDM state update. */
pvr_csb_emit (csb, VDMCTRL_PDS_STATE0, state0) {
state0.usc_target = PVRX(VDMCTRL_USC_TARGET_ANY);
@@ -6228,7 +6231,7 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
pvr_csb_emit (csb, VDMCTRL_PDS_STATE1, state1) {
const uint32_t data_offset =
pds_bo->vma->dev_addr.addr +
pds_bo->dev_addr.addr +
PVR_DW_TO_BYTES(pds_prog.program.code_size_aligned) -
cmd_buffer->device->heaps.pds_heap->base_addr.addr;
@@ -6239,7 +6242,7 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
pvr_csb_emit (csb, VDMCTRL_PDS_STATE2, state2) {
const uint32_t code_offset =
pds_bo->vma->dev_addr.addr -
pds_bo->dev_addr.addr -
cmd_buffer->device->heaps.pds_heap->base_addr.addr;
state2.pds_code_addr = PVR_DEV_ADDR(code_offset);
@@ -6260,7 +6263,7 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
if (result != VK_SUCCESS)
return result;
dummy_stream = dummy_bo->bo->map;
dummy_stream = pvr_bo_suballoc_get_map_addr(dummy_bo);
/* For indexed draw cmds fill in the dummy's header (as it won't change
* based on the indirect args) and increment by the in-use size of each
@@ -6277,18 +6280,16 @@ pvr_write_draw_indirect_vdm_stream(struct pvr_cmd_buffer *cmd_buffer,
pvr_csb_pack (dummy_stream, VDMCTRL_STREAM_RETURN, word);
/* clang-format on */
pvr_bo_cpu_unmap(cmd_buffer->device, dummy_bo);
/* Stream link to the first dummy which forces the VDM to discard any
* prefetched (dummy) control stream.
*/
pvr_csb_emit (csb, VDMCTRL_STREAM_LINK0, link) {
link.with_return = true;
link.link_addrmsb = dummy_bo->vma->dev_addr;
link.link_addrmsb = dummy_bo->dev_addr;
}
pvr_csb_emit (csb, VDMCTRL_STREAM_LINK1, link) {
link.link_addrlsb = dummy_bo->vma->dev_addr;
link.link_addrlsb = dummy_bo->dev_addr;
}
/* Point the pds program to the next argument buffer and the next VDM
@@ -6744,9 +6745,10 @@ pvr_execute_deferred_cmd_buffer(struct pvr_cmd_buffer *cmd_buffer,
prim_db_elems + cmd->dbsc2.state.depthbias_index;
uint32_t *const addr =
cmd->dbsc2.ppp_cs_bo->bo->map + cmd->dbsc2.patch_offset;
pvr_bo_suballoc_get_map_addr(cmd->dbsc2.ppp_cs_bo) +
cmd->dbsc2.patch_offset;
assert(cmd->dbsc2.ppp_cs_bo->bo->map);
assert(pvr_bo_suballoc_get_map_addr(cmd->dbsc2.ppp_cs_bo));
pvr_csb_pack (addr, TA_STATE_ISPDBSC, ispdbsc) {
ispdbsc.dbindex = db_idx;

33
src/imagination/vulkan/pvr_device.c
View File

@@ -110,6 +110,7 @@
*/
#define PVR_SUBALLOCATOR_GENERAL_SIZE (128 * 1024)
#define PVR_SUBALLOCATOR_PDS_SIZE (128 * 1024)
#define PVR_SUBALLOCATOR_TRANSFER_SIZE (128 * 1024)
#define PVR_SUBALLOCATOR_USC_SIZE (128 * 1024)
struct pvr_drm_device_info {
@@ -1814,6 +1815,10 @@ VkResult pvr_CreateDevice(VkPhysicalDevice physicalDevice,
device->heaps.pds_heap,
device,
PVR_SUBALLOCATOR_PDS_SIZE);
pvr_bo_suballocator_init(&device->suballoc_transfer,
device->heaps.transfer_3d_heap,
device,
PVR_SUBALLOCATOR_TRANSFER_SIZE);
pvr_bo_suballocator_init(&device->suballoc_usc,
device->heaps.usc_heap,
device,
@@ -1926,6 +1931,7 @@ err_dec_device_count:
p_atomic_dec(&device->instance->active_device_count);
pvr_bo_suballocator_fini(&device->suballoc_usc);
pvr_bo_suballocator_fini(&device->suballoc_transfer);
pvr_bo_suballocator_fini(&device->suballoc_pds);
pvr_bo_suballocator_fini(&device->suballoc_general);
@@ -1968,6 +1974,7 @@ void pvr_DestroyDevice(VkDevice _device,
pvr_bo_suballoc_free(device->nop_program.usc);
pvr_free_list_destroy(device->global_free_list);
pvr_bo_suballocator_fini(&device->suballoc_usc);
pvr_bo_suballocator_fini(&device->suballoc_transfer);
pvr_bo_suballocator_fini(&device->suballoc_pds);
pvr_bo_suballocator_fini(&device->suballoc_general);
pvr_bo_store_destroy(device);
@@ -2524,6 +2531,8 @@ VkResult pvr_gpu_upload(struct pvr_device *device,
allocator = &device->suballoc_general;
else if (heap == device->heaps.pds_heap)
allocator = &device->suballoc_pds;
else if (heap == device->heaps.transfer_3d_heap)
allocator = &device->suballoc_transfer;
else if (heap == device->heaps.usc_heap)
allocator = &device->suballoc_usc;
else
@@ -2547,30 +2556,18 @@ VkResult pvr_gpu_upload_usc(struct pvr_device *device,
uint64_t code_alignment,
struct pvr_suballoc_bo **const pvr_bo_out)
{
struct pvr_suballoc_bo *suballoc_bo = NULL;
VkResult result;
void *map;
assert(code_size > 0);
/* The USC will prefetch the next instruction, so over allocate by 1
* instruction to prevent reading off the end of a page into a potentially
* unallocated page.
*/
result = pvr_bo_suballoc(&device->suballoc_usc,
code_size + ROGUE_MAX_INSTR_BYTES,
code_alignment,
false,
&suballoc_bo);
if (result != VK_SUCCESS)
return result;
map = pvr_bo_suballoc_get_map_addr(suballoc_bo);
memcpy(map, code, code_size);
*pvr_bo_out = suballoc_bo;
return VK_SUCCESS;
return pvr_gpu_upload(device,
device->heaps.usc_heap,
code,
code_size + ROGUE_MAX_INSTR_BYTES,
code_alignment,
pvr_bo_out);
}
/**

56
src/imagination/vulkan/pvr_job_transfer.c
View File

@@ -2094,8 +2094,9 @@ pvr_pds_unitex(const struct pvr_device_info *dev_info,
&ctx->pds_unitex_code[program->num_texture_dma_kicks]
[program->num_uniform_dma_kicks];
struct pvr_transfer_3d_state *state = &prep_data->state;
struct pvr_bo *pvr_bo;
struct pvr_suballoc_bo *pvr_bo;
VkResult result;
void *map;
/* Uniform program is not used. */
assert(program->num_uniform_dma_kicks == 0U);
@@ -2128,13 +2129,10 @@ pvr_pds_unitex(const struct pvr_device_info *dev_info,
return result;
state->tex_state_data_offset =
pvr_bo->vma->dev_addr.addr - ctx->device->heaps.pds_heap->base_addr.addr;
pvr_bo->dev_addr.addr - ctx->device->heaps.pds_heap->base_addr.addr;
pvr_pds_generate_pixel_shader_sa_texture_state_data(program,
pvr_bo->bo->map,
dev_info);
pvr_bo_cpu_unmap(transfer_cmd->cmd_buffer->device, pvr_bo);
map = pvr_bo_suballoc_get_map_addr(pvr_bo);
pvr_pds_generate_pixel_shader_sa_texture_state_data(program, map, dev_info);
/* Save the dev_addr and size in the 3D state. */
state->uni_tex_code_offset = unitex_code->code_offset;
@@ -2761,7 +2759,7 @@ static VkResult pvr_3d_copy_blit_core(struct pvr_transfer_ctx *ctx,
const struct pvr_tq_frag_sh_reg_layout *sh_reg_layout;
struct pvr_pds_pixel_shader_sa_program unitex_prog = { 0U };
uint32_t tex_state_dma_size_dw;
struct pvr_bo *pvr_bo;
struct pvr_suballoc_bo *pvr_bo;
uint32_t *dma_space;
result = pvr_pbe_src_format(transfer_cmd, state, &state->shader_props);
@@ -2843,7 +2841,7 @@ static VkResult pvr_3d_copy_blit_core(struct pvr_transfer_ctx *ctx,
if (result != VK_SUCCESS)
return result;
dma_space = (uint32_t *)pvr_bo->bo->map;
dma_space = (uint32_t *)pvr_bo_suballoc_get_map_addr(pvr_bo);
result = pvr_sampler_image_state(ctx,
transfer_cmd,
@@ -2879,7 +2877,7 @@ static VkResult pvr_3d_copy_blit_core(struct pvr_transfer_ctx *ctx,
unitex_prog.texture_dma_address,
state->common_ptr,
tex_state_dma_size_dw,
pvr_bo->vma->dev_addr.addr,
pvr_bo->dev_addr.addr,
true,
dev_info);
@@ -2994,7 +2992,7 @@ pvr_pds_coeff_task(struct pvr_transfer_ctx *ctx,
{
struct pvr_transfer_3d_state *state = &prep_data->state;
struct pvr_pds_coeff_loading_program program = { 0U };
struct pvr_bo *pvr_bo;
struct pvr_suballoc_bo *pvr_bo;
VkResult result;
program.num_fpu_iterators = 1U;
@@ -3041,9 +3039,10 @@ pvr_pds_coeff_task(struct pvr_transfer_ctx *ctx,
return result;
state->pds_coeff_task_offset =
pvr_bo->vma->dev_addr.addr - ctx->device->heaps.pds_heap->base_addr.addr;
pvr_bo->dev_addr.addr - ctx->device->heaps.pds_heap->base_addr.addr;
pvr_pds_generate_coeff_loading_program(&program, pvr_bo->bo->map);
pvr_pds_generate_coeff_loading_program(&program,
pvr_bo_suballoc_get_map_addr(pvr_bo));
state->coeff_data_size = program.data_size;
state->pds_temps = program.temps_used;
@@ -3952,13 +3951,13 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
struct pvr_winsys_transfer_regs *const regs = &state->regs;
struct pvr_transfer_pass *pass = NULL;
uint32_t flags = transfer_cmd->flags;
struct pvr_suballoc_bo *pvr_cs_bo;
pvr_dev_addr_t stream_base_vaddr;
uint32_t num_prim_blks = 0U;
uint32_t prim_blk_size = 0U;
uint32_t region_arrays_size;
uint32_t num_region_arrays;
uint32_t total_stream_size;
struct pvr_bo *pvr_cs_bo;
bool was_linked = false;
uint32_t rem_mappings;
uint32_t num_sources;
@@ -4039,10 +4038,10 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
return result;
stream_base_vaddr =
PVR_DEV_ADDR(pvr_cs_bo->vma->dev_addr.addr -
PVR_DEV_ADDR(pvr_cs_bo->dev_addr.addr -
ctx->device->heaps.transfer_3d_heap->base_addr.addr);
cs_ptr = pvr_cs_bo->bo->map;
cs_ptr = pvr_bo_suballoc_get_map_addr(pvr_cs_bo);
blk_cs_ptr = cs_ptr + region_arrays_size / sizeof(uint32_t);
source = 0;
@@ -4119,9 +4118,9 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
struct pvr_tq_layer_properties *layer = &shader_props->layer_props;
const struct pvr_tq_frag_sh_reg_layout *sh_reg_layout;
enum pvr_transfer_pbe_pixel_src pbe_src_format;
struct pvr_suballoc_bo *pvr_bo;
uint32_t tex_state_dma_size;
pvr_dev_addr_t dev_offset;
struct pvr_bo *pvr_bo;
/* Reset the shared register bank ptrs each src implies new texture
* state (Note that we don't change texture state per prim block).
@@ -4239,7 +4238,7 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
state->filter[source],
sh_reg_layout,
0U,
pvr_bo->bo->map);
pvr_bo_suballoc_get_map_addr(pvr_bo));
if (result != VK_SUCCESS)
return result;
@@ -4252,7 +4251,7 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
sh_reg_layout,
state,
0U,
pvr_bo->bo->map);
pvr_bo_suballoc_get_map_addr(pvr_bo));
if (result != VK_SUCCESS)
return result;
@@ -4260,16 +4259,20 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
unitex_pds_prog.texture_dma_address,
state->common_ptr,
tex_state_dma_size,
pvr_bo->vma->dev_addr.addr,
pvr_bo->dev_addr.addr,
true,
dev_info);
state->common_ptr += tex_state_dma_size;
pvr_write_usc_constants(sh_reg_layout, pvr_bo->bo->map);
pvr_write_usc_constants(sh_reg_layout,
pvr_bo_suballoc_get_map_addr(pvr_bo));
if (pvr_pick_component_needed(&state->custom_mapping))
pvr_dma_texel_unwind(state, sh_reg_layout, pvr_bo->bo->map);
if (pvr_pick_component_needed(&state->custom_mapping)) {
pvr_dma_texel_unwind(state,
sh_reg_layout,
pvr_bo_suballoc_get_map_addr(pvr_bo));
}
}
result = pvr_pds_unitex(dev_info,
@@ -4323,7 +4326,7 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
}
cs_ptr =
(uint32_t *)pvr_cs_bo->bo->map +
(uint32_t *)pvr_bo_suballoc_get_map_addr(pvr_cs_bo) +
num_region_arrays * PVRX(IPF_CONTROL_STREAM_SIZE_DWORDS);
free_ctrl_stream_words = PVRX(IPF_CONTROL_STREAM_SIZE_DWORDS);
@@ -4337,7 +4340,8 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
prim_blk_addr = stream_base_vaddr;
prim_blk_addr.addr +=
(uintptr_t)blk_cs_ptr - (uintptr_t)pvr_cs_bo->bo->map;
(uintptr_t)blk_cs_ptr -
(uintptr_t)pvr_bo_suballoc_get_map_addr(pvr_cs_bo);
result = pvr_isp_primitive_block(dev_info,
ctx,
@@ -4479,7 +4483,7 @@ static VkResult pvr_isp_ctrl_stream(const struct pvr_device_info *dev_info,
pvr_csb_pack (&regs->isp_mtile_base, CR_ISP_MTILE_BASE, reg) {
reg.addr =
PVR_DEV_ADDR(pvr_cs_bo->vma->dev_addr.addr -
PVR_DEV_ADDR(pvr_cs_bo->dev_addr.addr -
ctx->device->heaps.transfer_3d_heap->base_addr.addr);
}

5
src/imagination/vulkan/pvr_private.h
View File

@@ -202,6 +202,7 @@ struct pvr_device {
struct pvr_suballocator suballoc_general;
struct pvr_suballocator suballoc_pds;
struct pvr_suballocator suballoc_transfer;
struct pvr_suballocator suballoc_usc;
struct {
@@ -704,7 +705,7 @@ struct pvr_deferred_cs_command {
struct {
struct pvr_ppp_dbsc state;
struct pvr_bo *ppp_cs_bo;
struct pvr_suballoc_bo *ppp_cs_bo;
uint32_t patch_offset;
} dbsc2;
};
@@ -1292,7 +1293,7 @@ VkResult pvr_cmd_buffer_alloc_mem(struct pvr_cmd_buffer *cmd_buffer,
struct pvr_winsys_heap *heap,
uint64_t size,
uint32_t flags,
struct pvr_bo **const pvr_bo_out);
struct pvr_suballoc_bo **const pvr_bo_out);
void pvr_calculate_vertex_cam_size(const struct pvr_device_info *dev_info,
const uint32_t vs_output_size,

10
src/imagination/vulkan/pvr_query_compute.c
View File

@@ -200,10 +200,10 @@ static VkResult pvr_write_compute_query_pds_data_section(
struct pvr_private_compute_pipeline *pipeline)
{
const struct pvr_pds_info *const info = &query_prog->info;
struct pvr_suballoc_bo *pvr_bo;
const uint8_t *entries;
uint32_t *dword_buffer;
uint64_t *qword_buffer;
struct pvr_bo *pvr_bo;
VkResult result;
result = pvr_cmd_buffer_alloc_mem(cmd_buffer,
@@ -214,8 +214,8 @@ static VkResult pvr_write_compute_query_pds_data_section(
if (result != VK_SUCCESS)
return result;
dword_buffer = (uint32_t *)pvr_bo->bo->map;
qword_buffer = (uint64_t *)pvr_bo->bo->map;
dword_buffer = (uint32_t *)pvr_bo_suballoc_get_map_addr(pvr_bo);
qword_buffer = (uint64_t *)pvr_bo_suballoc_get_map_addr(pvr_bo);
entries = (uint8_t *)info->entries;
@@ -302,11 +302,9 @@ static VkResult pvr_write_compute_query_pds_data_section(
}
pipeline->pds_shared_update_data_offset =
pvr_bo->vma->dev_addr.addr -
pvr_bo->dev_addr.addr -
cmd_buffer->device->heaps.pds_heap->base_addr.addr;
pvr_bo_cpu_unmap(cmd_buffer->device, pvr_bo);
return VK_SUCCESS;
}