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i965: Share the predicate field between FS and VS.

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Note that BRW_PREDICATE_NONE is 0 and BRW_PREDICATE_NORMAL is 1, so that's a
lot like the true/false we had in the FS before.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Eric Anholt
2012-10-03 13:23:05 -07:00
parent 7abfb67dc4
commit 54679fcbca
13 changed files with 32 additions and 33 deletions
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4
src/mesa/drivers/dri/i965/brw_cfg.cpp
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@@ -171,7 +171,7 @@ cfg_t::cfg_t(fs_visitor *v)
next = new_block(); next = new_block();
next->start = (fs_inst *)inst->next; next->start = (fs_inst *)inst->next;
if (inst->predicated) if (inst->predicate)
cur->add_successor(mem_ctx, next); cur->add_successor(mem_ctx, next);
set_next_block(next); set_next_block(next);
@@ -182,7 +182,7 @@ cfg_t::cfg_t(fs_visitor *v)
next = new_block(); next = new_block();
next->start = (fs_inst *)inst->next; next->start = (fs_inst *)inst->next;
if (inst->predicated) if (inst->predicate)
cur->add_successor(mem_ctx, next); cur->add_successor(mem_ctx, next);
set_next_block(next); set_next_block(next);

16
src/mesa/drivers/dri/i965/brw_fs.cpp
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@@ -141,7 +141,7 @@ fs_inst::equals(fs_inst *inst)
src[1].equals(inst->src[1]) && src[1].equals(inst->src[1]) &&
src[2].equals(inst->src[2]) && src[2].equals(inst->src[2]) &&
saturate == inst->saturate && saturate == inst->saturate &&
predicated == inst->predicated && predicate == inst->predicate &&
conditional_mod == inst->conditional_mod && conditional_mod == inst->conditional_mod &&
mlen == inst->mlen && mlen == inst->mlen &&
base_mrf == inst->base_mrf && base_mrf == inst->base_mrf &&
@@ -736,7 +736,7 @@ fs_visitor::emit_general_interpolation(ir_variable *ir)
emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS, attr); emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS, attr);
fs_inst *inst = emit_linterp(attr, fs_reg(interp), fs_inst *inst = emit_linterp(attr, fs_reg(interp),
interpolation_mode, false); interpolation_mode, false);
inst->predicated = true; inst->predicate = BRW_PREDICATE_NORMAL;
inst->predicate_inverse = true; inst->predicate_inverse = true;
} }
if (intel->gen < 6) { if (intel->gen < 6) {
@@ -1351,7 +1351,7 @@ fs_visitor::register_coalesce_2()
fs_inst *inst = (fs_inst *)node; fs_inst *inst = (fs_inst *)node;
if (inst->opcode != BRW_OPCODE_MOV || if (inst->opcode != BRW_OPCODE_MOV ||
inst->predicated || inst->predicate ||
inst->saturate || inst->saturate ||
inst->src[0].file != GRF || inst->src[0].file != GRF ||
inst->src[0].negate || inst->src[0].negate ||
@@ -1431,7 +1431,7 @@ fs_visitor::register_coalesce()
continue; continue;
if (inst->opcode != BRW_OPCODE_MOV || if (inst->opcode != BRW_OPCODE_MOV ||
inst->predicated || inst->predicate ||
inst->saturate || inst->saturate ||
inst->dst.file != GRF || (inst->src[0].file != GRF && inst->dst.file != GRF || (inst->src[0].file != GRF &&
inst->src[0].file != UNIFORM)|| inst->src[0].file != UNIFORM)||
@@ -1532,7 +1532,7 @@ fs_visitor::compute_to_mrf()
next_ip++; next_ip++;
if (inst->opcode != BRW_OPCODE_MOV || if (inst->opcode != BRW_OPCODE_MOV ||
inst->predicated || inst->predicate ||
inst->dst.file != MRF || inst->src[0].file != GRF || inst->dst.file != MRF || inst->src[0].file != GRF ||
inst->dst.type != inst->src[0].type || inst->dst.type != inst->src[0].type ||
inst->src[0].abs || inst->src[0].negate || inst->src[0].smear != -1) inst->src[0].abs || inst->src[0].negate || inst->src[0].smear != -1)
@@ -1581,7 +1581,7 @@ fs_visitor::compute_to_mrf()
* that writes that reg, but it would require smarter * that writes that reg, but it would require smarter
* tracking to delay the rewriting until complete success. * tracking to delay the rewriting until complete success.
*/ */
if (scan_inst->predicated) if (scan_inst->predicate)
break; break;
/* If it's half of register setup and not the same half as /* If it's half of register setup and not the same half as
@@ -1758,7 +1758,7 @@ fs_visitor::remove_duplicate_mrf_writes()
if (inst->opcode == BRW_OPCODE_MOV && if (inst->opcode == BRW_OPCODE_MOV &&
inst->dst.file == MRF && inst->dst.file == MRF &&
inst->src[0].file == GRF && inst->src[0].file == GRF &&
!inst->predicated) { !inst->predicate) {
last_mrf_move[inst->dst.reg] = inst; last_mrf_move[inst->dst.reg] = inst;
} }
} }
@@ -1788,7 +1788,7 @@ fs_visitor::get_instruction_generating_reg(fs_inst *start,
fs_reg reg) fs_reg reg)
{ {
if (end == start || if (end == start ||
end->predicated || end->predicate ||
end->force_uncompressed || end->force_uncompressed ||
end->force_sechalf || end->force_sechalf ||
!reg.equals(end->dst)) { !reg.equals(end->dst)) {

2
src/mesa/drivers/dri/i965/brw_fs.h
View File

@@ -158,8 +158,6 @@ public:
fs_reg dst; fs_reg dst;
fs_reg src[3]; fs_reg src[3];
bool saturate; bool saturate;
bool predicated;
bool predicate_inverse;
int conditional_mod; /**< BRW_CONDITIONAL_* */ int conditional_mod; /**< BRW_CONDITIONAL_* */
int mlen; /**< SEND message length */ int mlen; /**< SEND message length */

2
src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
View File

@@ -253,7 +253,7 @@ fs_visitor::opt_copy_propagate_local(void *mem_ctx, bblock_t *block)
inst->src[0].file == IMM) && inst->src[0].file == IMM) &&
inst->src[0].type == inst->dst.type && inst->src[0].type == inst->dst.type &&
!inst->saturate && !inst->saturate &&
!inst->predicated && !inst->predicate &&
!inst->force_uncompressed && !inst->force_uncompressed &&
!inst->force_sechalf && !inst->force_sechalf &&
inst->src[0].smear == -1) { inst->src[0].smear == -1) {

2
src/mesa/drivers/dri/i965/brw_fs_cse.cpp
View File

@@ -92,7 +92,7 @@ fs_visitor::opt_cse_local(bblock_t *block, exec_list *aeb)
inst = (fs_inst *) inst->next) { inst = (fs_inst *) inst->next) {
/* Skip some cases. */ /* Skip some cases. */
if (is_expression(inst) && !inst->predicated && inst->mlen == 0 && if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
!inst->force_uncompressed && !inst->force_sechalf && !inst->force_uncompressed && !inst->force_sechalf &&
!inst->conditional_mod) !inst->conditional_mod)
{ {

2
src/mesa/drivers/dri/i965/brw_fs_emit.cpp
View File

@@ -803,7 +803,7 @@ fs_visitor::generate_code()
dst = brw_reg_from_fs_reg(&inst->dst); dst = brw_reg_from_fs_reg(&inst->dst);
brw_set_conditionalmod(p, inst->conditional_mod); brw_set_conditionalmod(p, inst->conditional_mod);
brw_set_predicate_control(p, inst->predicated); brw_set_predicate_control(p, inst->predicate);
brw_set_predicate_inverse(p, inst->predicate_inverse); brw_set_predicate_inverse(p, inst->predicate_inverse);
brw_set_saturate(p, inst->saturate); brw_set_saturate(p, inst->saturate);

10
src/mesa/drivers/dri/i965/brw_fs_fp.cpp
View File

@@ -93,7 +93,7 @@ fs_visitor::emit_fp_sop(uint32_t conditional_mod,
inst->conditional_mod = conditional_mod; inst->conditional_mod = conditional_mod;
inst = emit(BRW_OPCODE_SEL, regoffset(dst, i), one, fs_reg(0.0f)); inst = emit(BRW_OPCODE_SEL, regoffset(dst, i), one, fs_reg(0.0f));
inst->predicated = true; inst->predicate = BRW_PREDICATE_NORMAL;
} }
} }
} }
@@ -177,7 +177,7 @@ fs_visitor::emit_fragment_program_code()
inst = emit(BRW_OPCODE_SEL, regoffset(dst, i), inst = emit(BRW_OPCODE_SEL, regoffset(dst, i),
regoffset(src[1], i), regoffset(src[2], i)); regoffset(src[1], i), regoffset(src[2], i));
inst->predicated = true; inst->predicate = BRW_PREDICATE_NORMAL;
} }
} }
break; break;
@@ -261,7 +261,7 @@ fs_visitor::emit_fragment_program_code()
inst->conditional_mod = BRW_CONDITIONAL_L; inst->conditional_mod = BRW_CONDITIONAL_L;
inst = emit(BRW_OPCODE_IF); inst = emit(BRW_OPCODE_IF);
inst->predicated = true; inst->predicate = BRW_PREDICATE_NORMAL;
emit(FS_OPCODE_DISCARD); emit(FS_OPCODE_DISCARD);
emit(BRW_OPCODE_ENDIF); emit(BRW_OPCODE_ENDIF);
} }
@@ -300,7 +300,7 @@ fs_visitor::emit_fragment_program_code()
if (fpi->DstReg.WriteMask & WRITEMASK_Y) { if (fpi->DstReg.WriteMask & WRITEMASK_Y) {
emit(BRW_OPCODE_MOV, regoffset(dst, 1), regoffset(src[0], 0)); emit(BRW_OPCODE_MOV, regoffset(dst, 1), regoffset(src[0], 0));
inst = emit(BRW_OPCODE_MOV, regoffset(dst, 1), fs_reg(0.0f)); inst = emit(BRW_OPCODE_MOV, regoffset(dst, 1), fs_reg(0.0f));
inst->predicated = true; inst->predicate = BRW_PREDICATE_NORMAL;
} }
if (fpi->DstReg.WriteMask & WRITEMASK_Z) { if (fpi->DstReg.WriteMask & WRITEMASK_Z) {
@@ -308,7 +308,7 @@ fs_visitor::emit_fragment_program_code()
regoffset(src[0], 1), regoffset(src[0], 3)); regoffset(src[0], 1), regoffset(src[0], 3));
inst = emit(BRW_OPCODE_MOV, regoffset(dst, 2), fs_reg(0.0f)); inst = emit(BRW_OPCODE_MOV, regoffset(dst, 2), fs_reg(0.0f));
inst->predicated = true; inst->predicate = BRW_PREDICATE_NORMAL;
} }
} }

2
src/mesa/drivers/dri/i965/brw_fs_live_variables.cpp
View File

@@ -78,7 +78,7 @@ fs_live_variables::setup_def_use()
*/ */
if (inst->dst.file == GRF && if (inst->dst.file == GRF &&
inst->regs_written() == v->virtual_grf_sizes[inst->dst.reg] && inst->regs_written() == v->virtual_grf_sizes[inst->dst.reg] &&
!inst->predicated && !inst->predicate &&
!inst->force_uncompressed && !inst->force_uncompressed &&
!inst->force_sechalf) { !inst->force_sechalf) {
int reg = inst->dst.reg; int reg = inst->dst.reg;

2
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
View File

@@ -408,7 +408,7 @@ fs_visitor::spill_reg(int spill_reg)
* inst->regs_written(), then we need to unspill the destination * inst->regs_written(), then we need to unspill the destination
* since we write back out all of the regs_written(). * since we write back out all of the regs_written().
*/ */
if (inst->predicated || inst->force_uncompressed || inst->force_sechalf) { if (inst->predicate || inst->force_uncompressed || inst->force_sechalf) {
fs_reg unspill_reg = inst->dst; fs_reg unspill_reg = inst->dst;
for (int chan = 0; chan < inst->regs_written(); chan++) { for (int chan = 0; chan < inst->regs_written(); chan++) {
emit_unspill(inst, unspill_reg, emit_unspill(inst, unspill_reg,

4
src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
View File

@@ -298,7 +298,7 @@ instruction_scheduler::calculate_deps()
add_dep(last_mrf_write[inst->base_mrf + i], n); add_dep(last_mrf_write[inst->base_mrf + i], n);
} }
if (inst->predicated) { if (inst->predicate) {
assert(last_conditional_mod); assert(last_conditional_mod);
add_dep(last_conditional_mod, n); add_dep(last_conditional_mod, n);
} }
@@ -382,7 +382,7 @@ instruction_scheduler::calculate_deps()
add_dep(n, last_mrf_write[inst->base_mrf + i], 2); add_dep(n, last_mrf_write[inst->base_mrf + i], 2);
} }
if (inst->predicated) { if (inst->predicate) {
add_dep(n, last_conditional_mod); add_dep(n, last_conditional_mod);
} }

14
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
View File

@@ -191,7 +191,7 @@ fs_visitor::emit_minmax(uint32_t conditionalmod, fs_reg dst,
inst->conditional_mod = conditionalmod; inst->conditional_mod = conditionalmod;
inst = emit(BRW_OPCODE_SEL, dst, src0, src1); inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
inst->predicated = true; inst->predicate = BRW_PREDICATE_NORMAL;
} }
} }
@@ -329,12 +329,12 @@ fs_visitor::visit(ir_expression *ir)
inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f));
inst->conditional_mod = BRW_CONDITIONAL_G; inst->conditional_mod = BRW_CONDITIONAL_G;
inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f));
inst->predicated = true; inst->predicate = BRW_PREDICATE_NORMAL;
inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f));
inst->conditional_mod = BRW_CONDITIONAL_L; inst->conditional_mod = BRW_CONDITIONAL_L;
inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f));
inst->predicated = true; inst->predicate = BRW_PREDICATE_NORMAL;
break; break;
case ir_unop_rcp: case ir_unop_rcp:
@@ -623,7 +623,7 @@ fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r,
if (predicated || !l.equals(r)) { if (predicated || !l.equals(r)) {
fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); fs_inst *inst = emit(BRW_OPCODE_MOV, l, r);
inst->predicated = predicated; inst->predicate = predicated ? BRW_PREDICATE_NORMAL : BRW_PREDICATE_NONE;
} }
l.reg_offset++; l.reg_offset++;
@@ -724,7 +724,7 @@ fs_visitor::visit(ir_assignment *ir)
if (ir->write_mask & (1 << i)) { if (ir->write_mask & (1 << i)) {
inst = emit(BRW_OPCODE_MOV, l, r); inst = emit(BRW_OPCODE_MOV, l, r);
if (ir->condition) if (ir->condition)
inst->predicated = true; inst->predicate = BRW_PREDICATE_NORMAL;
r.reg_offset++; r.reg_offset++;
} }
l.reg_offset++; l.reg_offset++;
@@ -1673,7 +1673,7 @@ fs_visitor::visit(ir_if *ir)
emit_bool_to_cond_code(ir->condition); emit_bool_to_cond_code(ir->condition);
inst = emit(BRW_OPCODE_IF); inst = emit(BRW_OPCODE_IF);
inst->predicated = true; inst->predicate = BRW_PREDICATE_NORMAL;
} }
foreach_list(node, &ir->then_instructions) { foreach_list(node, &ir->then_instructions) {
@@ -1730,7 +1730,7 @@ fs_visitor::visit(ir_loop *ir)
inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); inst->conditional_mod = brw_conditional_for_comparison(ir->cmp);
inst = emit(BRW_OPCODE_BREAK); inst = emit(BRW_OPCODE_BREAK);
inst->predicated = true; inst->predicate = BRW_PREDICATE_NORMAL;
} }
foreach_list(node, &ir->body_instructions) { foreach_list(node, &ir->body_instructions) {

3
src/mesa/drivers/dri/i965/brw_shader.h
View File

@@ -30,6 +30,9 @@
class backend_instruction : public exec_node { class backend_instruction : public exec_node {
public: public:
enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */ enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
uint32_t predicate;
bool predicate_inverse;
}; };
class backend_visitor : public ir_visitor { class backend_visitor : public ir_visitor {

2
src/mesa/drivers/dri/i965/brw_vec4.h
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@@ -171,8 +171,6 @@ public:
src_reg src[3]; src_reg src[3];
bool saturate; bool saturate;
bool predicate_inverse;
uint32_t predicate;
int conditional_mod; /**< BRW_CONDITIONAL_* */ int conditional_mod; /**< BRW_CONDITIONAL_* */