diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c index a099431ccc6..e4b0b3df529 100644 --- a/src/intel/blorp/blorp_clear.c +++ b/src/intel/blorp/blorp_clear.c @@ -255,7 +255,6 @@ get_fast_clear_rect(const struct isl_device *dev, unreachable("Unsupported tiling format"); } } else { - assert(aux_surf->usage == ISL_SURF_USAGE_CCS_BIT); /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render * Target(s)", beneath the "Fast Color Clear" bullet (p327): * @@ -270,9 +269,25 @@ get_fast_clear_rect(const struct isl_device *dev, * The alignment size in the table that follows is a multiple of the * alignment size that is baked into the CCS surface format. */ - x_align = isl_format_get_layout(aux_surf->format)->bw * 16; - y_align = isl_format_get_layout(aux_surf->format)->bh * 32 / - isl_format_get_layout(aux_surf->format)->bpb; + enum isl_format ccs_format; + if (ISL_GFX_VERX10(dev) == 120) { + assert(surf->tiling == ISL_TILING_Y0); + switch (isl_format_get_layout(surf->format)->bpb) { + case 8: ccs_format = ISL_FORMAT_GFX12_CCS_8BPP_Y0; break; + case 16: ccs_format = ISL_FORMAT_GFX12_CCS_16BPP_Y0; break; + case 32: ccs_format = ISL_FORMAT_GFX12_CCS_32BPP_Y0; break; + case 64: ccs_format = ISL_FORMAT_GFX12_CCS_64BPP_Y0; break; + case 128: ccs_format = ISL_FORMAT_GFX12_CCS_128BPP_Y0; break; + default: unreachable("Invalid surface bpb for fast clearing"); + } + } else { + assert(aux_surf->usage == ISL_SURF_USAGE_CCS_BIT); + ccs_format = aux_surf->format; + } + + x_align = isl_format_get_layout(ccs_format)->bw * 16; + y_align = isl_format_get_layout(ccs_format)->bh * 32 / + isl_format_get_layout(ccs_format)->bpb; /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render * Target(s)", beneath the "Fast Color Clear" bullet (p327):