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intel/fs: Implement the new load/store_scratch intrinsics

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This commit fills in a number of different pieces:

 1. We add support to brw_nir_lower_mem_access_bit_sizes to handle the
    new intrinsics.  This involves simple plumbing work as well as a
    tiny bit of extra logic to always scalarize scratch intrinsics

 2. Add code to brw_fs_nir.cpp to turn nir_load/store_scratch intrinsics
    into byte/dword scattered read/write messages which use the A32
    stateless model.

 3. Add code to lower_surface_logical_send to handle dword scattered
    messages and the A32 stateless model.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
This commit is contained in:
Jason Ekstrand
2019-02-28 08:15:30 -06:00
committed by Jason Ekstrand
parent e2297699de
commit 53bfcdeecf
5 changed files with 241 additions and 17 deletions
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4
src/intel/compiler/brw_fs.h
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@@ -228,6 +228,9 @@ public:
nir_intrinsic_instr *instr);
fs_reg get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld,
nir_intrinsic_instr *instr);
fs_reg swizzle_nir_scratch_addr(const brw::fs_builder &bld,
const fs_reg &addr,
bool in_dwords);
void nir_emit_intrinsic(const brw::fs_builder &bld,
nir_intrinsic_instr *instr);
void nir_emit_tes_intrinsic(const brw::fs_builder &bld,
@@ -341,6 +344,7 @@ public:
int *push_constant_loc;
fs_reg subgroup_id;
fs_reg scratch_base;
fs_reg frag_depth;
fs_reg frag_stencil;
fs_reg sample_mask;