nv50,nvc0: activate seamless cube map filtering
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@@ -89,7 +89,10 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_TEXTURE_SHADOW_MAP:
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case PIPE_CAP_NPOT_TEXTURES:
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case PIPE_CAP_ANISOTROPIC_FILTER:
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return 1;
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case PIPE_CAP_SEAMLESS_CUBE_MAP:
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return nv50_screen(pscreen)->tesla->grclass >= NVA0_3D;
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case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
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return 0;
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case PIPE_CAP_TWO_SIDED_STENCIL:
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case PIPE_CAP_DEPTH_CLAMP:
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case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
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@@ -417,6 +420,11 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
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BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
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OUT_RING (chan, 1);
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if (tesla_class >= NVA0_3D) {
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BEGIN_RING(chan, RING_3D_(NVA0_3D_TEX_MISC), 1);
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OUT_RING (chan, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
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}
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BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
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OUT_RING (chan, 0);
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BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
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@@ -34,6 +34,36 @@
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#include "nouveau/nouveau_gldefs.h"
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/* Caveats:
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* ! pipe_sampler_state.normalized_coords is ignored - rectangle textures will
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* use non-normalized coordinates, everything else won't
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* (The relevant bit is in the TIC entry and not the TSC entry.)
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*
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* ! pipe_sampler_state.seamless_cube_map is ignored - seamless filtering is
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* always activated on NVA0 +
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* (Give me the global bit, otherwise it's not worth the CPU work.)
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*
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* ! pipe_sampler_state.border_color is not swizzled according to the texture
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* swizzle in pipe_sampler_view
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* (This will be ugly with indirect independent texture/sampler access,
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* we'd have to emulate the logic in the shader. GL doesn't have that,
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* D3D doesn't have swizzle, if we knew what we were implementing we'd be
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* good.)
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*
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* ! pipe_rasterizer_state.line_last_pixel is ignored - it is never drawn
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*
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* ! pipe_rasterizer_state.flatshade_first also applies to QUADS
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* (There's a GL query for that, forcing an exception is just ridiculous.)
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*
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* ! pipe_rasterizer_state.gl_rasterization_rules is ignored - pixel centers
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* are always at half integer coordinates and the top-left rule applies
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* (There does not seem to be a hardware switch for this.)
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*
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* ! pipe_rasterizer_state.sprite_coord_enable is masked with 0xff on NVC0
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* (The hardware only has 8 slots meant for TexCoord and we have to assign
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* in advance to maintain elegant separate shader objects.)
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*/
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static INLINE uint32_t
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nv50_colormask(unsigned mask)
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{
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@@ -74,7 +74,10 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_TEXTURE_SHADOW_MAP:
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case PIPE_CAP_NPOT_TEXTURES:
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case PIPE_CAP_ANISOTROPIC_FILTER:
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case PIPE_CAP_SEAMLESS_CUBE_MAP:
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return 1;
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case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
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return 0;
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case PIPE_CAP_TWO_SIDED_STENCIL:
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case PIPE_CAP_DEPTH_CLAMP:
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case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
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@@ -441,6 +444,8 @@ nvc0_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
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OUT_RING (chan, 1);
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BEGIN_RING(chan, RING_3D(BLEND_ENABLE_COMMON), 1);
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OUT_RING (chan, 0);
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BEGIN_RING(chan, RING_3D(TEX_MISC), 1);
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OUT_RING (chan, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
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nvc0_magic_3d_init(chan);
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