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radeonsi: set PA_SU_VTX_CNTL consecutively with PA_CL_GB_VERT_CLIP_ADJ

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because they are all next to each other.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
This commit is contained in:
Marek Olšák
2023-02-18 00:36:23 -05:00
committed by Marge Bot
parent 429f43f088
commit 52f5b7a970
3 changed files with 35 additions and 9 deletions
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26
src/gallium/drivers/radeonsi/si_build_pm4.h
View File

@@ -246,6 +246,32 @@
} \
} while (0)
/**
* Set 5 consecutive registers if any register value is different.
*/
#define radeon_opt_set_context_reg5(sctx, offset, reg, val0, val1, val2, val3, val4) do { \
unsigned __value0 = (val0), __value1 = (val1), __value2 = (val2), __value3 = (val3), __value4 = (val4); \
if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1f) != 0x1f || \
sctx->tracked_regs.reg_value[(reg) + 0] != __value0 || \
sctx->tracked_regs.reg_value[(reg) + 1] != __value1 || \
sctx->tracked_regs.reg_value[(reg) + 2] != __value2 || \
sctx->tracked_regs.reg_value[(reg) + 3] != __value3 || \
sctx->tracked_regs.reg_value[(reg) + 4] != __value4) { \
radeon_set_context_reg_seq(offset, 5); \
radeon_emit(__value0); \
radeon_emit(__value1); \
radeon_emit(__value2); \
radeon_emit(__value3); \
radeon_emit(__value4); \
sctx->tracked_regs.reg_value[(reg) + 0] = __value0; \
sctx->tracked_regs.reg_value[(reg) + 1] = __value1; \
sctx->tracked_regs.reg_value[(reg) + 2] = __value2; \
sctx->tracked_regs.reg_value[(reg) + 3] = __value3; \
sctx->tracked_regs.reg_value[(reg) + 4] = __value4; \
sctx->tracked_regs.reg_saved |= 0x1full << (reg); \
} \
} while (0)
/**
* Set consecutive registers if any registers value is different.
*/

4
src/gallium/drivers/radeonsi/si_state.h
View File

@@ -279,13 +279,13 @@ enum si_tracked_reg
SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL,
SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ, /* 4 consecutive registers */
SI_TRACKED_PA_SU_VTX_CNTL, /* 5 consecutive registers */
SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ,
SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ,
SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ,
SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ,
SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
SI_TRACKED_PA_SU_VTX_CNTL,
SI_TRACKED_PA_SC_CLIPRECT_RULE,

14
src/gallium/drivers/radeonsi/si_state_viewport.c
View File

@@ -382,17 +382,17 @@ static void si_emit_guardband(struct si_context *ctx)
* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
*/
radeon_begin(&ctx->gfx_cs);
radeon_opt_set_context_reg4(ctx, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ,
SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ, fui(guardband_y), fui(discard_y),
radeon_opt_set_context_reg5(ctx, R_028BE4_PA_SU_VTX_CNTL, SI_TRACKED_PA_SU_VTX_CNTL,
S_028BE4_PIX_CENTER(rs->half_pixel_center) |
S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH +
vp_as_scissor.quant_mode),
fui(guardband_y), fui(discard_y),
fui(guardband_x), fui(discard_x));
radeon_opt_set_context_reg(ctx, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET,
SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
S_028234_HW_SCREEN_OFFSET_X(hw_screen_offset_x >> 4) |
S_028234_HW_SCREEN_OFFSET_Y(hw_screen_offset_y >> 4));
radeon_opt_set_context_reg(
ctx, R_028BE4_PA_SU_VTX_CNTL, SI_TRACKED_PA_SU_VTX_CNTL,
S_028BE4_PIX_CENTER(rs->half_pixel_center) | S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH + vp_as_scissor.quant_mode));
S_028234_HW_SCREEN_OFFSET_Y(hw_screen_offset_y >> 4));
radeon_end_update_context_roll(ctx);
}