From 52b781760d92db64259b9ed8f10bc4d05cacba1f Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Fri, 5 Aug 2022 13:50:59 +0100 Subject: [PATCH] radv: enable ac_nir_lower_resinfo for ACO fossil-db (navi21): Totals from 4022 (2.98% of 134913) affected shaders: VGPRs: 207824 -> 205264 (-1.23%); split: -1.25%, +0.02% CodeSize: 18486240 -> 18778488 (+1.58%); split: -0.00%, +1.58% MaxWaves: 84398 -> 84882 (+0.57%) Instrs: 3408968 -> 3470936 (+1.82%); split: -0.00%, +1.82% Latency: 43493420 -> 43168394 (-0.75%); split: -1.57%, +0.82% InvThroughput: 6911341 -> 6816816 (-1.37%); split: -1.41%, +0.05% VClause: 88256 -> 82728 (-6.26%); split: -6.31%, +0.04% SClause: 130061 -> 131526 (+1.13%); split: -0.39%, +1.51% Copies: 219849 -> 238548 (+8.51%); split: -0.05%, +8.56% Branches: 79168 -> 79174 (+0.01%); split: -0.00%, +0.01% PreSGPRs: 180683 -> 184952 (+2.36%); split: -0.17%, +2.53% PreVGPRs: 179716 -> 178956 (-0.42%) Signed-off-by: Rhys Perry Reviewed-by: Georg Lehmann Part-of: --- src/amd/vulkan/radv_nir_apply_pipeline_layout.c | 15 ++++++++++++++- src/amd/vulkan/radv_nir_lower_ycbcr_textures.c | 2 ++ src/amd/vulkan/radv_pipeline.c | 8 ++++---- 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_nir_apply_pipeline_layout.c b/src/amd/vulkan/radv_nir_apply_pipeline_layout.c index b4ab9f62416..62b884e2598 100644 --- a/src/amd/vulkan/radv_nir_apply_pipeline_layout.c +++ b/src/amd/vulkan/radv_nir_apply_pipeline_layout.c @@ -366,7 +366,13 @@ update_image_intrinsic(nir_builder *b, apply_layout_state *state, nir_intrinsic_ nir_ssa_def *desc = get_sampler_desc( b, state, deref, dim == GLSL_SAMPLER_DIM_BUF ? AC_DESC_BUFFER : AC_DESC_IMAGE, nir_intrinsic_access(intrin) & ACCESS_NON_UNIFORM, NULL, !is_load); - nir_rewrite_image_intrinsic(intrin, desc, true); + + if (intrin->intrinsic == nir_intrinsic_image_deref_descriptor_amd) { + nir_ssa_def_rewrite_uses(&intrin->dest.ssa, desc); + nir_instr_remove(&intrin->instr); + } else { + nir_rewrite_image_intrinsic(intrin, desc, true); + } } static void @@ -429,6 +435,7 @@ apply_layout_to_intrin(nir_builder *b, apply_layout_state *state, nir_intrinsic_ case nir_intrinsic_image_deref_atomic_dec_wrap: case nir_intrinsic_image_deref_size: case nir_intrinsic_image_deref_samples: + case nir_intrinsic_image_deref_descriptor_amd: update_image_intrinsic(b, state, intrin); break; default: @@ -507,6 +514,12 @@ apply_layout_to_tex(nir_builder *b, apply_layout_state *state, nir_tex_instr *te } } + if (tex->op == nir_texop_descriptor_amd) { + nir_ssa_def_rewrite_uses(&tex->dest.ssa, image); + nir_instr_remove(&tex->instr); + return; + } + for (unsigned i = 0; i < tex->num_srcs; i++) { switch (tex->src[i].src_type) { case nir_tex_src_texture_deref: diff --git a/src/amd/vulkan/radv_nir_lower_ycbcr_textures.c b/src/amd/vulkan/radv_nir_lower_ycbcr_textures.c index e5a38b23f3e..931e1e29a85 100644 --- a/src/amd/vulkan/radv_nir_lower_ycbcr_textures.c +++ b/src/amd/vulkan/radv_nir_lower_ycbcr_textures.c @@ -56,6 +56,8 @@ get_texture_size(struct ycbcr_state *state, nir_deref_instr *texture) nir_ssa_dest_init(&tex->instr, &tex->dest, nir_tex_instr_dest_size(tex), 32, NULL); nir_builder_instr_insert(b, &tex->instr); + state->builder->shader->info.uses_resource_info_query = true; + return nir_i2f32(b, &tex->dest.ssa); } diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index ad4f65cc31b..2d9e89acf05 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -4321,6 +4321,10 @@ radv_postprocess_nir(struct radv_pipeline *pipeline, } NIR_PASS(_, stage->nir, radv_nir_lower_ycbcr_textures, pipeline_layout); + + if (stage->nir->info.uses_resource_info_query) + NIR_PASS(_, stage->nir, ac_nir_lower_resinfo, gfx_level); + NIR_PASS_V(stage->nir, radv_nir_apply_pipeline_layout, device, pipeline_layout, &stage->info, &stage->args); @@ -4353,10 +4357,6 @@ radv_postprocess_nir(struct radv_pipeline *pipeline, if (lowered_ngg) radv_lower_ngg(device, stage, pipeline_key); - if (radv_use_llvm_for_stage(device, stage->stage) && - stage->nir->info.uses_resource_info_query) - NIR_PASS(_, stage->nir, ac_nir_lower_resinfo, gfx_level); - NIR_PASS(_, stage->nir, ac_nir_lower_global_access); NIR_PASS_V(stage->nir, radv_nir_lower_abi, gfx_level, &stage->info, &stage->args, pipeline_key, radv_use_llvm_for_stage(device, stage->stage));