intel/compiler: Use nir_lower_tex_options::lower_offset_filter for tg4 on XeHP
Based on Rafael's: * "nir/lower_tex: Add option to lower offset for tg4 too." * "intel/compiler: Lower offsets for tg4 on gen9+." * "WIP: Do not lower basic offsets." * "WIP: intel/compiler: Enable lowering offsets restriction." But, with these changes: * Fixed range checking to be signed 4 bits * Converted to filter * Apply only to gfx12.5+ * Use nir_src_is_const / nir_src_comp_as_int (s-b Jason) Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14142>
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@@ -746,6 +746,34 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *data)
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}
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}
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/* On gfx12.5+, if the offsets are not both constant and in the {-8,7} range,
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* we will have nir_lower_tex() lower the source offset by returning true from
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* this filter function.
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*/
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static bool
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lower_xehp_tg4_offset_filter(const nir_instr *instr, UNUSED const void *data)
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{
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if (instr->type != nir_instr_type_tex)
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return false;
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nir_tex_instr *tex = nir_instr_as_tex(instr);
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if (tex->op != nir_texop_tg4)
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return false;
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int offset_index = nir_tex_instr_src_index(tex, nir_tex_src_offset);
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if (offset_index < 0)
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return false;
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if (!nir_src_is_const(tex->src[offset_index].src))
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return true;
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int64_t offset_x = nir_src_comp_as_int(tex->src[offset_index].src, 0);
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int64_t offset_y = nir_src_comp_as_int(tex->src[offset_index].src, 1);
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return offset_x < -8 || offset_x > 7 || offset_y < -8 || offset_y > 7;
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}
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/* Does some simple lowering and runs the standard suite of optimizations
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*
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* This is intended to be called more-or-less directly after you get the
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@@ -792,6 +820,8 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
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.lower_txd_offset_clamp = true,
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.lower_tg4_offsets = true,
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.lower_txs_lod = true, /* Wa_14012320009 */
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.lower_offset_filter =
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devinfo->verx10 >= 125 ? lower_xehp_tg4_offset_filter : NULL,
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};
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OPT(nir_lower_tex, &tex_options);
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