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iris/anv: move Wa_14018912822 as a drirc workaround

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This should be toggled on only for applications that hit the issue.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9886
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25424>
This commit is contained in:
Tapani Pälli
2023-09-27 12:04:18 +03:00
committed by Marge Bot
parent ebe95fee21
commit 524e8865ce
8 changed files with 17 additions and 2 deletions
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1
src/gallium/drivers/iris/driinfo_iris.h
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@@ -6,6 +6,7 @@ DRI_CONF_SECTION_DEBUG
DRI_CONF_ALWAYS_FLUSH_CACHE(false)
DRI_CONF_OPT_B(sync_compile, false, "Always compile synchronously (will cause stalls)")
DRI_CONF_LIMIT_TRIG_INPUT_RANGE(false)
DRI_CONF_INTEL_ENABLE_WA_14018912822(false)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_PERFORMANCE

2
src/gallium/drivers/iris/iris_screen.c
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@@ -874,6 +874,8 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
driQueryOptionb(config->options, "limit_trig_input_range");
screen->driconf.lower_depth_range_rate =
driQueryOptionf(config->options, "lower_depth_range_rate");
screen->driconf.intel_enable_wa_14018912822 =
driQueryOptionb(config->options, "intel_enable_wa_14018912822");
screen->precompile = debug_get_bool_option("shader_precompile", true);

1
src/gallium/drivers/iris/iris_screen.h
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@@ -188,6 +188,7 @@ struct iris_screen {
bool sync_compile;
bool limit_trig_input_range;
float lower_depth_range_rate;
bool intel_enable_wa_14018912822;
} driconf;
/** Does the kernel support various features (KERNEL_HAS_* bitfield)? */

3
src/gallium/drivers/iris/iris_state.c
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@@ -6426,8 +6426,9 @@ iris_upload_dirty_render_state(struct iris_context *ice,
* CONST_COLOR, CONST_ALPHA and supply zero by using blend constants.
*/
bool needs_wa_14018912822 =
screen->driconf.intel_enable_wa_14018912822 &&
intel_needs_workaround(batch->screen->devinfo, 14018912822) &&
util_framebuffer_get_num_samples(&ice->state.framebuffer) > 1;
util_framebuffer_get_num_samples(&ice->state.framebuffer) > 1;
if (dirty & IRIS_DIRTY_CC_VIEWPORT) {
const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;

3
src/intel/vulkan/anv_device.c
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@@ -82,6 +82,7 @@ static const driOptionDescription anv_dri_options[] = {
DRI_CONF_ANV_FP64_WORKAROUND_ENABLED(false)
DRI_CONF_ANV_GENERATED_INDIRECT_THRESHOLD(4)
DRI_CONF_NO_16BIT(false)
DRI_CONF_INTEL_ENABLE_WA_14018912822(false)
DRI_CONF_ANV_QUERY_CLEAR_WITH_BLORP_THRESHOLD(6)
DRI_CONF_ANV_QUERY_COPY_WITH_SHADER_THRESHOLD(6)
DRI_CONF_ANV_FORCE_INDIRECT_DESCRIPTORS(false)
@@ -1557,6 +1558,8 @@ anv_init_dri_options(struct anv_instance *instance)
driQueryOptionf(&instance->dri_options, "lower_depth_range_rate");
instance->no_16bit =
driQueryOptionb(&instance->dri_options, "no_16bit");
instance->intel_enable_wa_14018912822 =
driQueryOptionb(&instance->dri_options, "intel_enable_wa_14018912822");
instance->mesh_conv_prim_attrs_to_vert_attrs =
driQueryOptioni(&instance->dri_options, "anv_mesh_conv_prim_attrs_to_vert_attrs");
instance->fp64_workaround_enabled =

1
src/intel/vulkan/anv_private.h
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@@ -1059,6 +1059,7 @@ struct anv_instance {
/* HW workarounds */
bool no_16bit;
bool intel_enable_wa_14018912822;
};
VkResult anv_init_wsi(struct anv_physical_device *physical_device);

4
src/intel/vulkan/genX_gfx_state.c
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@@ -304,6 +304,7 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer)
const struct vk_dynamic_graphics_state *dyn =
&cmd_buffer->vk.dynamic_graphics_state;
struct anv_gfx_dynamic_state *hw_state = &gfx->dyn_state;
struct anv_instance *instance = cmd_buffer->device->physical->instance;
#define GET(field) hw_state->field
#define SET(bit, field, value) \
@@ -853,7 +854,8 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer)
dyn->cb.attachments[i].dst_alpha_blend_factor];
}
if (intel_needs_workaround(cmd_buffer->device->info, 14018912822) &&
if (instance->intel_enable_wa_14018912822 &&
intel_needs_workaround(cmd_buffer->device->info, 14018912822) &&
pipeline->rasterization_samples > 1) {
if (DestinationBlendFactor == BLENDFACTOR_ZERO) {
DestinationBlendFactor = BLENDFACTOR_CONST_COLOR;

4
src/util/driconf.h
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@@ -324,6 +324,10 @@
DRI_CONF_OPT_B(fake_sparse, def, \
"Advertise support for sparse binding of textures regardless of real support")
#define DRI_CONF_INTEL_ENABLE_WA_14018912822(def) \
DRI_CONF_OPT_B(intel_enable_wa_14018912822, def, \
"Intel workaround for using zero blend constants")
/**
* \brief Image quality-related options
*/