diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index d496da87842..68460b7bc24 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1624,7 +1624,7 @@ radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer, struct radv_graphics_p
       radv_emit_shader_prefetch(cmd_buffer, cmd_buffer->state.shaders[MESA_SHADER_MESH]);
 
    if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
-      si_cp_dma_prefetch(cmd_buffer, state->vb_va, pipeline->vb_desc_alloc_size);
+      si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
 
    if (mask & RADV_PREFETCH_TCS)
       radv_emit_shader_prefetch(cmd_buffer, cmd_buffer->state.shaders[MESA_SHADER_TESS_CTRL]);
@@ -4888,13 +4888,13 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
    assert(!cmd_buffer->state.mesh_shading);
 
    struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
+   unsigned vb_desc_alloc_size = util_bitcount(vs->info.vs.vb_desc_usage_mask) * 16;
    unsigned vb_offset;
    void *vb_ptr;
    uint64_t va;
 
    /* allocate some descriptor state for vertex buffers */
-   if (!radv_cmd_buffer_upload_alloc(cmd_buffer, pipeline->vb_desc_alloc_size, &vb_offset,
-                                     &vb_ptr))
+   if (!radv_cmd_buffer_upload_alloc(cmd_buffer, vb_desc_alloc_size, &vb_offset, &vb_ptr))
       return;
 
    radv_write_vertex_descriptors(cmd_buffer, pipeline, false, vb_ptr);
@@ -4906,6 +4906,7 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
                               AC_UD_VS_VERTEX_BUFFERS, va);
 
    cmd_buffer->state.vb_va = va;
+   cmd_buffer->state.vb_size = vb_desc_alloc_size;
    cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
 
    if (unlikely(cmd_buffer->device->trace_bo))
diff --git a/src/amd/vulkan/radv_device_generated_commands.c b/src/amd/vulkan/radv_device_generated_commands.c
index e6c33a866d6..56072e730b1 100644
--- a/src/amd/vulkan/radv_device_generated_commands.c
+++ b/src/amd/vulkan/radv_device_generated_commands.c
@@ -1183,11 +1183,13 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer,
    };
 
    if (layout->bind_vbo_mask) {
+      uint32_t mask = vertex_shader->info.vs.vb_desc_usage_mask;
+      unsigned vb_desc_alloc_size = util_bitcount(mask) * 16;
+
       radv_write_vertex_descriptors(cmd_buffer, graphics_pipeline, true, upload_data);
 
-      uint32_t *vbo_info = (uint32_t *)((char *)upload_data + graphics_pipeline->vb_desc_alloc_size);
+      uint32_t *vbo_info = (uint32_t *)((char *)upload_data + vb_desc_alloc_size);
 
-      uint32_t mask = vertex_shader->info.vs.vb_desc_usage_mask;
       unsigned idx = 0;
       while (mask) {
          unsigned i = u_bit_scan(&mask);
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index fbe284e3dbd..b3e8734e4d5 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4409,8 +4409,6 @@ radv_pipeline_init_vertex_input_state(const struct radv_device *device,
       }
    }
 
-   pipeline->vb_desc_alloc_size = util_bitcount(vs_info->vs.vb_desc_usage_mask) * 16;
-
    /* Prepare the VS input state for prologs created inside a library. */
    if (vs_info->vs.has_prolog && !(pipeline->dynamic_states & RADV_DYNAMIC_VERTEX_INPUT)) {
       const enum amd_gfx_level gfx_level = pdevice->rad_info.gfx_level;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index d01b489020b..2e4f8424700 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1580,6 +1580,7 @@ struct radv_multisample_state {
 struct radv_cmd_state {
    /* Vertex descriptors */
    uint64_t vb_va;
+   unsigned vb_size;
 
    bool predicating;
    uint64_t dirty;
@@ -2239,7 +2240,6 @@ struct radv_graphics_pipeline {
    uint8_t attrib_bindings[MAX_VERTEX_ATTRIBS];
    uint32_t attrib_ends[MAX_VERTEX_ATTRIBS];
    uint32_t attrib_index_offset[MAX_VERTEX_ATTRIBS];
-   uint32_t vb_desc_alloc_size;
    uint32_t pa_sc_mode_cntl_1;
    uint32_t db_render_control;