radv: Determine tcs_in_out_eq in radv_pipeline instead of the compiler.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>

src/amd/compiler/aco_instruction_selection_setup.cpp

@@ -443,28 +443,8 @@ void setup_gs_variables(isel_context *ctx, nir_shader *nir)
 void
 setup_tcs_info(isel_context *ctx, nir_shader *nir, nir_shader *vs)
 {
-   /* When the number of TCS input and output vertices are the same (typically 3):
+   ctx->tcs_in_out_eq = ctx->args->shader_info->vs.tcs_in_out_eq;
-    * - There is an equal amount of LS and HS invocations
+   ctx->tcs_temp_only_inputs = ctx->args->shader_info->vs.tcs_temp_only_input_mask;
-    * - In case of merged LSHS shaders, the LS and HS halves of the shader
-    *   always process the exact same vertex. We can use this knowledge to optimize them.
-    *
-    * We don't set tcs_in_out_eq if the float controls differ because that might
-    * involve different float modes for the same block and our optimizer
-    * doesn't handle a instruction dominating another with a different mode.
-    */
-   ctx->tcs_in_out_eq =
-      ctx->stage == vertex_tess_control_hs &&
-      ctx->args->options->key.tcs.input_vertices == nir->info.tess.tcs_vertices_out &&
-      vs->info.float_controls_execution_mode == nir->info.float_controls_execution_mode;
-
-   if (ctx->tcs_in_out_eq) {
-      ctx->tcs_temp_only_inputs = ~nir->info.tess.tcs_cross_invocation_inputs_read &
-                                  ~nir->info.inputs_read_indirectly &
-                                  ~vs->info.outputs_accessed_indirectly &
-                                  nir->info.inputs_read &
-                                  vs->info.outputs_written;
-   }
-
    ctx->tcs_num_inputs = ctx->program->info->tcs.num_linked_inputs;
    ctx->tcs_num_outputs = ctx->program->info->tcs.num_linked_outputs;
    ctx->tcs_num_patch_outputs = ctx->program->info->tcs.num_linked_patch_outputs;

src/amd/vulkan/radv_pipeline.c

@@ -3351,7 +3351,35 @@ VkResult radv_create_shaders(struct radv_pipeline *pipeline,
 			}
 			NIR_PASS_V(nir[i], nir_lower_memory_model);
 
-			if (i == MESA_SHADER_TESS_CTRL) {
+			if (i == MESA_SHADER_VERTEX) {
+				if (nir[MESA_SHADER_TESS_CTRL] && !radv_use_llvm_for_stage(device, i)) {
+					/* When the number of TCS input and output vertices are the same (typically 3):
+					 * - There is an equal amount of LS and HS invocations
+					 * - In case of merged LSHS shaders, the LS and HS halves of the shader
+					 *   always process the exact same vertex. We can use this knowledge to optimize them.
+					 *
+					 * We don't set tcs_in_out_eq if the float controls differ because that might
+					 * involve different float modes for the same block and our optimizer
+					 * doesn't handle a instruction dominating another with a different mode.
+					 */
+					infos[i].vs.tcs_in_out_eq =
+					 	device->physical_device->rad_info.chip_class >= GFX9 &&
+						pipeline_key->tess_input_vertices == nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out &&
+						nir[MESA_SHADER_VERTEX]->info.float_controls_execution_mode == nir[MESA_SHADER_TESS_CTRL]->info.float_controls_execution_mode;
+
+					if (infos[i].vs.tcs_in_out_eq)
+						infos[i].vs.tcs_temp_only_input_mask =
+							nir[MESA_SHADER_TESS_CTRL]->info.inputs_read &
+							nir[MESA_SHADER_VERTEX]->info.outputs_written &
+							~nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_cross_invocation_inputs_read &
+							~nir[MESA_SHADER_TESS_CTRL]->info.inputs_read_indirectly &
+							~nir[MESA_SHADER_VERTEX]->info.outputs_accessed_indirectly;
+
+					/* Copy data to TCS so it can be accessed by the backend if they are merged. */
+					infos[MESA_SHADER_TESS_CTRL].vs.tcs_in_out_eq = infos[i].vs.tcs_in_out_eq;
+					infos[MESA_SHADER_TESS_CTRL].vs.tcs_temp_only_input_mask = infos[i].vs.tcs_temp_only_input_mask;
+				}
+			} else if (i == MESA_SHADER_TESS_CTRL) {
 				/* Copy correct primitive mode from TES info. */
 				nir[i]->info.tess.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
 

src/amd/vulkan/radv_shader.h

@@ -270,6 +270,8 @@ struct radv_shader_info {
 		bool as_es;
 		bool as_ls;
 		bool export_prim_id;
+		bool tcs_in_out_eq;
+		uint64_t tcs_temp_only_input_mask;
 		uint8_t num_linked_outputs;
 	} vs;
 	struct {