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anv: flush tile cache independent of format with HIZ-CCS flush

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Cc: mesa-stable
Fixes: ba87656079 ("anv: implement undocumented tile cache flush requirements")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10420
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10530
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27440>
This commit is contained in:
Tapani Pälli
2024-01-31 13:39:50 +02:00
committed by Marge Bot
parent af51e5f7a9
commit 5178ad761c
1 changed files with 14 additions and 20 deletions
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34
src/intel/vulkan/genX_cmd_buffer.c
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@@ -395,22 +395,18 @@ transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
0, base_layer, layer_count, ISL_AUX_OP_AMBIGUATE);
}
#if GFX_VER == 12
/* Depth/Stencil writes by the render pipeline to D16 & S8 formats use a
* different pairing bit for the compression cache line. This means that
* there is potential for aliasing with the wrong cache if you use another
* format OR a piece of HW that does not use the same pairing. To avoid
* this, flush the tile cache as the compression data does not live in the
* color/depth cache.
/* Additional tile cache flush for MTL:
*
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/10420
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/10530
*/
if (image->planes[depth_plane].aux_usage == ISL_AUX_USAGE_HIZ_CCS &&
final_needs_depth && !initial_depth_valid &&
anv_image_format_is_d16_or_s8(image)) {
if (intel_device_info_is_mtl(cmd_buffer->device->info) &&
image->planes[depth_plane].aux_usage == ISL_AUX_USAGE_HIZ_CCS &&
final_needs_depth && !initial_depth_valid) {
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_TILE_CACHE_FLUSH_BIT,
"D16 or S8 HIZ-CCS flush");
"HIZ-CCS flush");
}
#endif
}
/* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
@@ -467,17 +463,15 @@ transition_stencil_buffer(struct anv_cmd_buffer *cmd_buffer,
}
}
/* Depth/Stencil writes by the render pipeline to D16 & S8 formats use a
* different pairing bit for the compression cache line. This means that
* there is potential for aliasing with the wrong cache if you use another
* format OR a piece of HW that does not use the same pairing. To avoid
* this, flush the tile cache as the compression data does not live in the
* color/depth cache.
/* Additional tile cache flush for MTL:
*
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/10420
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/10530
*/
if (anv_image_format_is_d16_or_s8(image)) {
if (intel_device_info_is_mtl(cmd_buffer->device->info)) {
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_TILE_CACHE_FLUSH_BIT,
"D16 or S8 HIZ-CCS flush");
"HIZ-CCS flush");
}
#endif
}