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radv: only apply enable_mrt_output_nan_fixup for 32-bit float MRTs

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This is incorrect for 32-bit integer MRTs which are clamped to the
maximum value of the format, and returning 0 can break some shaders.

This fixes a rendering issue with RAGE2.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4329
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16080>
This commit is contained in:
Samuel Pitoiset
2022-04-21 12:41:27 +02:00
committed by Marge Bot
parent d839d37642
commit 5121e6dd7e
3 changed files with 24 additions and 18 deletions
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28
src/amd/vulkan/radv_pipeline.c
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@@ -60,6 +60,7 @@ struct radv_blend_state {
uint32_t spi_shader_col_format;
uint32_t col_format_is_int8;
uint32_t col_format_is_int10;
uint32_t col_format_is_float32;
uint32_t cb_shader_mask;
uint32_t db_alpha_to_mask;
@@ -529,6 +530,16 @@ format_is_int10(VkFormat format)
return false;
}
static bool
format_is_float32(VkFormat format)
{
const struct util_format_description *desc = vk_format_description(format);
int channel = vk_format_get_first_non_void_channel(format);
return channel >= 0 &&
desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT && desc->channel[channel].size == 32;
}
static void
radv_pipeline_compute_spi_color_formats(const struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
@@ -536,7 +547,7 @@ radv_pipeline_compute_spi_color_formats(const struct radv_pipeline *pipeline,
{
const VkPipelineRenderingCreateInfo *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
unsigned col_format = 0, is_int8 = 0, is_int10 = 0, is_float32 = 0;
unsigned num_targets;
for (unsigned i = 0; i < render_create_info->colorAttachmentCount; ++i) {
@@ -555,6 +566,8 @@ radv_pipeline_compute_spi_color_formats(const struct radv_pipeline *pipeline,
is_int8 |= 1 << i;
if (format_is_int10(fmt))
is_int10 |= 1 << i;
if (format_is_float32(fmt))
is_float32 |= 1 << i;
}
col_format |= cf << (4 * i);
@@ -590,6 +603,7 @@ radv_pipeline_compute_spi_color_formats(const struct radv_pipeline *pipeline,
blend->spi_shader_col_format = col_format;
blend->col_format_is_int8 = is_int8;
blend->col_format_is_int10 = is_int10;
blend->col_format_is_float32 = is_float32;
}
/*
@@ -3116,7 +3130,7 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline,
key.ps.lower_discard_to_demote = true;
if (pipeline->device->instance->enable_mrt_output_nan_fixup)
key.ps.enable_mrt_output_nan_fixup = true;
key.ps.enable_mrt_output_nan_fixup = blend->col_format_is_float32;
key.ps.force_vrs_enabled = pipeline->device->force_vrs_enabled;
@@ -3988,6 +4002,7 @@ radv_lower_fs_output(nir_shader *nir, const struct radv_pipeline_key *pipeline_k
unsigned col_format = (pipeline_key->ps.col_format >> (4 * slot)) & 0xf;
bool is_int8 = (pipeline_key->ps.is_int8 >> slot) & 1;
bool is_int10 = (pipeline_key->ps.is_int10 >> slot) & 1;
bool enable_mrt_output_nan_fixup = (pipeline_key->ps.enable_mrt_output_nan_fixup >> slot) & 1;
bool is_16bit = intrin->src[0].ssa->bit_size == 16;
if (col_format == V_028714_SPI_SHADER_ZERO)
@@ -4005,13 +4020,8 @@ radv_lower_fs_output(nir_shader *nir, const struct radv_pipeline_key *pipeline_k
}
}
/* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
if (pipeline_key->ps.enable_mrt_output_nan_fixup && !nir->info.internal && !is_16bit &&
(col_format == V_028714_SPI_SHADER_32_R ||
col_format == V_028714_SPI_SHADER_32_GR ||
col_format == V_028714_SPI_SHADER_32_AR ||
col_format == V_028714_SPI_SHADER_32_ABGR ||
col_format == V_028714_SPI_SHADER_FP16_ABGR)) {
/* Replace NaN by zero (for 32-bit float formats) to fix game bugs if requested. */
if (enable_mrt_output_nan_fixup && !nir->info.internal && !is_16bit) {
u_foreach_bit(i, write_mask) {
const bool save_exact = b.exact;