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anv: Handle end of pipe with MI_FLUSH_DW on transfer queue

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Blitter command streamer supports MI_FLUSH_DW command so make sure we
don't end up emitting pipe control with CS stall and also handle the end
of pipe timestamp with MI_FLUSH_DW command.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18325>
This commit is contained in:
Sagar Ghuge
2023-09-07 16:01:57 -07:00
committed by Marge Bot
parent b048ba569a
commit 5112b42146
3 changed files with 25 additions and 3 deletions
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3
src/intel/vulkan/anv_batch_chain.c
View File

@@ -833,6 +833,7 @@ anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer)
cmd_buffer->batch.allocated_batch_size = ANV_MIN_CMD_BUFFER_BATCH_SIZE;
cmd_buffer->batch.extend_cb = anv_cmd_buffer_chain_batch;
cmd_buffer->batch.engine_class = cmd_buffer->queue_family->engine_class;
anv_batch_bo_start(batch_bo, &cmd_buffer->batch,
GFX8_MI_BATCH_BUFFER_START_length * 4);
@@ -846,6 +847,8 @@ anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer)
cmd_buffer->generation_batch.user_data = cmd_buffer;
cmd_buffer->generation_batch.allocated_batch_size = 0;
cmd_buffer->generation_batch.extend_cb = anv_cmd_buffer_chain_generation_batch;
cmd_buffer->generation_batch.engine_class =
cmd_buffer->queue_family->engine_class;
int success = u_vector_init_pow2(&cmd_buffer->seen_bbos, 8,
sizeof(struct anv_bo *));

2
src/intel/vulkan/anv_private.h
View File

@@ -1897,6 +1897,8 @@ struct anv_batch {
* of the driver.
*/
VkResult status;
enum intel_engine_class engine_class;
};
void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);

23
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -8054,6 +8054,15 @@ void genX(cmd_emit_timestamp)(struct anv_batch *batch,
struct anv_address addr,
enum anv_timestamp_capture_type type,
void *data) {
/* Make sure ANV_TIMESTAMP_CAPTURE_AT_CS_STALL and
* ANV_TIMESTAMP_REWRITE_COMPUTE_WALKER capture type are not set for
* transfer queue.
*/
if (batch->engine_class == INTEL_ENGINE_CLASS_COPY) {
assert(type != ANV_TIMESTAMP_CAPTURE_AT_CS_STALL ||
type != ANV_TIMESTAMP_REWRITE_COMPUTE_WALKER);
}
switch (type) {
case ANV_TIMESTAMP_CAPTURE_TOP_OF_PIPE: {
struct mi_builder b;
@@ -8062,10 +8071,18 @@ void genX(cmd_emit_timestamp)(struct anv_batch *batch,
break;
}
case ANV_TIMESTAMP_CAPTURE_END_OF_PIPE:
genx_batch_emit_pipe_control_write
(batch, device->info, WriteTimestamp, addr, 0, 0);
case ANV_TIMESTAMP_CAPTURE_END_OF_PIPE: {
if (batch->engine_class == INTEL_ENGINE_CLASS_COPY) {
anv_batch_emit(batch, GENX(MI_FLUSH_DW), fd) {
fd.PostSyncOperation = WriteTimestamp;
fd.Address = addr;
}
} else {
genx_batch_emit_pipe_control_write(batch, device->info,
WriteTimestamp, addr, 0, 0);
}
break;
}
case ANV_TIMESTAMP_CAPTURE_AT_CS_STALL:
genx_batch_emit_pipe_control_write