From 50df855fbaaa6b0dee715553da9dd5839327fb19 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 29 May 2024 16:45:30 +0200 Subject: [PATCH] radv: update configuring SPI_SHADER_PGM_LO_ES on GFX12 Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/layers/radv_sqtt_layer.c | 18 +++++++++++++++--- src/amd/vulkan/radv_cmd_buffer.c | 14 +++++++++++--- 2 files changed, 26 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/layers/radv_sqtt_layer.c b/src/amd/vulkan/layers/radv_sqtt_layer.c index 6820a5519e3..eca1b718848 100644 --- a/src/amd/vulkan/layers/radv_sqtt_layer.c +++ b/src/amd/vulkan/layers/radv_sqtt_layer.c @@ -74,7 +74,11 @@ radv_sqtt_emit_relocated_shaders(struct radv_cmd_buffer *cmd_buffer, struct radv va = reloc->va[MESA_SHADER_TESS_EVAL]; if (tes->info.is_ngg) { - radeon_set_sh_reg(cs, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); + if (gfx_level >= GFX12) { + radeon_set_sh_reg(cs, R_00B224_SPI_SHADER_PGM_LO_ES, va >> 8); + } else { + radeon_set_sh_reg(cs, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); + } } else if (tes->info.tes.as_es) { radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2); radeon_emit(cs, va >> 8); @@ -92,7 +96,11 @@ radv_sqtt_emit_relocated_shaders(struct radv_cmd_buffer *cmd_buffer, struct radv va = reloc->va[MESA_SHADER_GEOMETRY]; if (gs->info.is_ngg) { - radeon_set_sh_reg(cs, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); + if (gfx_level >= GFX12) { + radeon_set_sh_reg(cs, R_00B224_SPI_SHADER_PGM_LO_ES, va >> 8); + } else { + radeon_set_sh_reg(cs, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); + } } else { if (gfx_level >= GFX9) { if (gfx_level >= GFX10) { @@ -121,7 +129,11 @@ radv_sqtt_emit_relocated_shaders(struct radv_cmd_buffer *cmd_buffer, struct radv if (pipeline->base.shaders[MESA_SHADER_MESH]) { va = reloc->va[MESA_SHADER_MESH]; - radeon_set_sh_reg(cs, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); + if (pdev->info.gfx_level >= GFX12) { + radeon_set_sh_reg(cs, R_00B224_SPI_SHADER_PGM_LO_ES, va >> 8); + } else { + radeon_set_sh_reg(cs, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); + } } } diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 9a518c72d02..d4b649a1199 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2046,7 +2046,11 @@ radv_emit_hw_ngg(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *e } if (!shader->info.merged_shader_compiled_separately) { - radeon_set_sh_reg(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); + if (pdev->info.gfx_level >= GFX12) { + radeon_set_sh_reg(cmd_buffer->cs, R_00B224_SPI_SHADER_PGM_LO_ES, va >> 8); + } else { + radeon_set_sh_reg(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8); + } radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2); radeon_emit(cmd_buffer->cs, shader->config.rsrc1); @@ -2192,7 +2196,9 @@ radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer) } else { radv_shader_combine_cfg_vs_gs(vs, next_stage, &rsrc1, &rsrc2); - if (pdev->info.gfx_level >= GFX10) { + if (pdev->info.gfx_level >= GFX12) { + radeon_set_sh_reg(cmd_buffer->cs, R_00B224_SPI_SHADER_PGM_LO_ES, vs->va >> 8); + } else if (pdev->info.gfx_level >= GFX10) { radeon_set_sh_reg(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, vs->va >> 8); } else { radeon_set_sh_reg(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, vs->va >> 8); @@ -5128,7 +5134,9 @@ emit_prolog_regs(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *v unsigned rsrc1_reg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; if (vs_shader->info.is_ngg || cmd_buffer->state.shaders[MESA_SHADER_GEOMETRY] == vs_shader || (vs_shader->info.merged_shader_compiled_separately && vs_shader->info.next_stage == MESA_SHADER_GEOMETRY)) { - pgm_lo_reg = chip >= GFX10 ? R_00B320_SPI_SHADER_PGM_LO_ES : R_00B210_SPI_SHADER_PGM_LO_ES; + pgm_lo_reg = chip >= GFX12 ? R_00B224_SPI_SHADER_PGM_LO_ES + : chip >= GFX10 ? R_00B320_SPI_SHADER_PGM_LO_ES + : R_00B210_SPI_SHADER_PGM_LO_ES; rsrc1_reg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; } else if (cmd_buffer->state.shaders[MESA_SHADER_TESS_CTRL] == vs_shader || (vs_shader->info.merged_shader_compiled_separately &&