Revert "intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WM"

This reverts commit 729de1488f.

It turns out that, although the register is in the logical context,
it isn't whitelisted, so we can't actually write it from userspace
batch buffers.  The write just becomes a noop, which is why we saw
no performance changes.

I manually whitelisted it, and still observed no performance gains, but
it did regress KHR-GL46.texture_cube_map_array.color_depth_attachments
on the iris driver.  So we might need to fix something before enabling
this.  To prevent it randomly getting turned on should the kernel ever
whitelist this register, we revert the patch for now.

src/intel/vulkan/genX_state.c

@@ -292,17 +292,6 @@ genX(init_device_state)(struct anv_device *device)
          lri.DataDWord      = cache_mode_0;
       }
    }
-
-   /* WA_220160979: Enable Hardware filtering of Semi-Pipelined State in WM. */
-   uint32_t common_slice_chicken4;
-   anv_pack_struct(&common_slice_chicken4, GENX(COMMON_SLICE_CHICKEN4),
-                   .EnableHardwareFilteringinWM = true,
-                   .EnableHardwareFilteringinWMMask = true);
-
-   anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
-      lri.RegisterOffset = GENX(COMMON_SLICE_CHICKEN4_num);
-      lri.DataDWord      = common_slice_chicken4;
-   }
 #endif
 
    /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so