tgsi: provide a way to encode memory qualifiers for SSBO
Each load/store on most hardware can specify what caching to do. Since SSBO allows individual variables to also have separate caching modes, allow loads/stores to have the qualifiers instead of attempting to encode them in declarations. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
@@ -620,6 +620,7 @@ tgsi_default_instruction( void )
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instruction.NumSrcRegs = 1;
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instruction.Label = 0;
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instruction.Texture = 0;
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instruction.Memory = 0;
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instruction.Padding = 0;
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return instruction;
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@@ -766,6 +767,34 @@ tgsi_build_instruction_texture(
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return instruction_texture;
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}
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static struct tgsi_instruction_memory
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tgsi_default_instruction_memory( void )
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{
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struct tgsi_instruction_memory instruction_memory;
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instruction_memory.Qualifier = 0;
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instruction_memory.Padding = 0;
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return instruction_memory;
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}
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static struct tgsi_instruction_memory
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tgsi_build_instruction_memory(
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unsigned qualifier,
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struct tgsi_token *prev_token,
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struct tgsi_instruction *instruction,
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struct tgsi_header *header )
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{
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struct tgsi_instruction_memory instruction_memory;
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instruction_memory.Qualifier = qualifier;
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instruction_memory.Padding = 0;
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instruction->Memory = 1;
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instruction_grow( instruction, header );
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return instruction_memory;
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}
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static struct tgsi_texture_offset
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tgsi_default_texture_offset( void )
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@@ -1012,6 +1041,7 @@ tgsi_default_full_instruction( void )
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full_instruction.Predicate = tgsi_default_instruction_predicate();
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full_instruction.Label = tgsi_default_instruction_label();
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full_instruction.Texture = tgsi_default_instruction_texture();
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full_instruction.Memory = tgsi_default_instruction_memory();
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for( i = 0; i < TGSI_FULL_MAX_TEX_OFFSETS; i++ ) {
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full_instruction.TexOffsets[i] = tgsi_default_texture_offset();
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}
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@@ -1123,6 +1153,24 @@ tgsi_build_full_instruction(
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prev_token = (struct tgsi_token *) texture_offset;
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}
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}
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if (full_inst->Instruction.Memory) {
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struct tgsi_instruction_memory *instruction_memory;
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if( maxsize <= size )
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return 0;
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instruction_memory =
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(struct tgsi_instruction_memory *) &tokens[size];
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size++;
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*instruction_memory = tgsi_build_instruction_memory(
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full_inst->Memory.Qualifier,
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prev_token,
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instruction,
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header );
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prev_token = (struct tgsi_token *) instruction_memory;
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}
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for( i = 0; i < full_inst->Instruction.NumDstRegs; i++ ) {
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const struct tgsi_full_dst_register *reg = &full_inst->Dst[i];
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struct tgsi_dst_register *dst_register;
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@@ -624,6 +624,16 @@ iter_instruction(
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}
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}
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if (inst->Instruction.Memory) {
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uint32_t qualifier = inst->Memory.Qualifier;
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while (qualifier) {
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int bit = ffs(qualifier) - 1;
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qualifier &= ~(1U << bit);
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TXT(", ");
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ENM(bit, tgsi_memory_names);
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}
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}
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switch (inst->Instruction.Opcode) {
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case TGSI_OPCODE_IF:
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case TGSI_OPCODE_UIF:
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@@ -195,6 +195,10 @@ tgsi_parse_token(
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}
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}
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if (inst->Instruction.Memory) {
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next_token(ctx, &inst->Memory);
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}
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assert( inst->Instruction.NumDstRegs <= TGSI_FULL_MAX_DST_REGISTERS );
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for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
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@@ -91,6 +91,7 @@ struct tgsi_full_instruction
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struct tgsi_instruction_predicate Predicate;
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struct tgsi_instruction_label Label;
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struct tgsi_instruction_texture Texture;
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struct tgsi_instruction_memory Memory;
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struct tgsi_full_dst_register Dst[TGSI_FULL_MAX_DST_REGISTERS];
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struct tgsi_full_src_register Src[TGSI_FULL_MAX_SRC_REGISTERS];
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struct tgsi_texture_offset TexOffsets[TGSI_FULL_MAX_TEX_OFFSETS];
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@@ -208,6 +208,13 @@ const char *tgsi_immediate_type_names[4] =
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"FLT64"
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};
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const char *tgsi_memory_names[3] =
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{
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"COHERENT",
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"RESTRICT",
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"VOLATILE",
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};
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static inline void
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tgsi_strings_check(void)
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@@ -60,6 +60,8 @@ extern const char *tgsi_fs_coord_pixel_center_names[2];
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extern const char *tgsi_immediate_type_names[4];
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extern const char *tgsi_memory_names[3];
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const char *
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tgsi_file_name(unsigned file);
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@@ -1039,6 +1039,12 @@ parse_instruction(
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inst.Texture.Texture = TGSI_TEXTURE_UNKNOWN;
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}
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if ((i >= TGSI_OPCODE_LOAD && i <= TGSI_OPCODE_ATOMIMAX) ||
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i == TGSI_OPCODE_RESQ) {
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inst.Instruction.Memory = 1;
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inst.Memory.Qualifier = 0;
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}
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/* Parse instruction operands.
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*/
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for (i = 0; i < info->num_dst + info->num_src + info->is_tex; i++) {
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@@ -1090,6 +1096,27 @@ parse_instruction(
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}
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inst.Texture.NumOffsets = i;
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cur = ctx->cur;
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eat_opt_white(&cur);
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for (i = 0; inst.Instruction.Memory && *cur == ','; i++) {
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uint j;
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cur++;
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eat_opt_white(&cur);
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ctx->cur = cur;
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for (j = 0; j < 3; j++) {
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if (str_match_nocase_whole(&ctx->cur, tgsi_memory_names[j])) {
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inst.Memory.Qualifier |= 1U << j;
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break;
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}
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}
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if (j == 3) {
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report_error(ctx, "Expected memory qualifier");
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return FALSE;
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}
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cur = ctx->cur;
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eat_opt_white(&cur);
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}
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cur = ctx->cur;
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eat_opt_white( &cur );
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if (info->is_branch && *cur == ':') {
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@@ -60,6 +60,7 @@ union tgsi_any_token {
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struct tgsi_instruction_predicate insn_predicate;
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struct tgsi_instruction_label insn_label;
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struct tgsi_instruction_texture insn_texture;
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struct tgsi_instruction_memory insn_memory;
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struct tgsi_texture_offset insn_texture_offset;
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struct tgsi_src_register src;
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struct tgsi_ind_register ind;
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@@ -1226,6 +1227,21 @@ ureg_emit_texture_offset(struct ureg_program *ureg,
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}
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void
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ureg_emit_memory(struct ureg_program *ureg,
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unsigned extended_token,
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unsigned qualifier)
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{
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union tgsi_any_token *out, *insn;
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out = get_tokens( ureg, DOMAIN_INSN, 1 );
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insn = retrieve_token( ureg, DOMAIN_INSN, extended_token );
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insn->insn.Memory = 1;
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out[0].value = 0;
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out[0].insn_memory.Qualifier = qualifier;
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}
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void
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ureg_fixup_insn_size(struct ureg_program *ureg,
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@@ -1378,6 +1394,42 @@ ureg_label_insn(struct ureg_program *ureg,
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}
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void
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ureg_memory_insn(struct ureg_program *ureg,
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unsigned opcode,
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const struct ureg_dst *dst,
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unsigned nr_dst,
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const struct ureg_src *src,
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unsigned nr_src,
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unsigned qualifier)
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{
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struct ureg_emit_insn_result insn;
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unsigned i;
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insn = ureg_emit_insn(ureg,
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opcode,
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FALSE,
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FALSE,
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FALSE,
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TGSI_SWIZZLE_X,
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TGSI_SWIZZLE_Y,
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TGSI_SWIZZLE_Z,
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TGSI_SWIZZLE_W,
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nr_dst,
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nr_src);
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ureg_emit_memory(ureg, insn.extended_token, qualifier);
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for (i = 0; i < nr_dst; i++)
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ureg_emit_dst(ureg, dst[i]);
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for (i = 0; i < nr_src; i++)
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ureg_emit_src(ureg, src[i]);
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ureg_fixup_insn_size(ureg, insn.insn_token);
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}
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static void
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emit_decl_semantic(struct ureg_program *ureg,
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unsigned file,
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@@ -531,6 +531,14 @@ ureg_label_insn(struct ureg_program *ureg,
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unsigned nr_src,
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unsigned *label);
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void
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ureg_memory_insn(struct ureg_program *ureg,
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unsigned opcode,
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const struct ureg_dst *dst,
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unsigned nr_dst,
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const struct ureg_src *src,
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unsigned nr_src,
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unsigned qualifier);
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/***********************************************************************
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* Internal instruction helpers, don't call these directly:
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@@ -568,6 +576,11 @@ void
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ureg_emit_texture_offset(struct ureg_program *ureg,
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const struct tgsi_texture_offset *offset);
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void
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ureg_emit_memory(struct ureg_program *ureg,
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unsigned insn_token,
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unsigned qualifier);
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void
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ureg_emit_dst( struct ureg_program *ureg,
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struct ureg_dst dst );
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@@ -572,7 +572,8 @@ struct tgsi_instruction
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unsigned Predicate : 1; /* BOOL */
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unsigned Label : 1;
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unsigned Texture : 1;
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unsigned Padding : 2;
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unsigned Memory : 1;
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unsigned Padding : 1;
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};
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/*
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@@ -729,6 +730,19 @@ struct tgsi_dst_register
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unsigned Padding : 6;
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};
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#define TGSI_MEMORY_COHERENT (1 << 0)
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#define TGSI_MEMORY_RESTRICT (1 << 1)
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#define TGSI_MEMORY_VOLATILE (1 << 2)
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/**
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* Specifies the type of memory access to do for the LOAD/STORE instruction.
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*/
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struct tgsi_instruction_memory
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{
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unsigned Qualifier : 3; /* TGSI_MEMORY_ */
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unsigned Padding : 29;
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};
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#ifdef __cplusplus
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}
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