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anv/image: Rename anv_image_plane::surface -> primary_surface

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This disambiguates code that accesses `image->planes[*].surface`.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>
This commit is contained in:
Chad Versace
2021-02-05 12:07:07 -08:00
committed by chadversary
parent e7844c552c
commit 5065faca00
5 changed files with 28 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/intel/vulkan/anv_blorp.c
View File

@@ -217,7 +217,7 @@ get_blorp_surf_for_anv_image(const struct anv_device *device,
(usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT) ?
ISL_SURF_USAGE_RENDER_TARGET_BIT : ISL_SURF_USAGE_TEXTURE_BIT;
const struct anv_surface *surface = &image->planes[plane].surface;
const struct anv_surface *surface = &image->planes[plane].primary_surface;
*blorp_surf = (struct blorp_surf) {
.surf = &surface->isl,
.addr = {

4
src/intel/vulkan/anv_device.c
View File

@@ -3892,9 +3892,9 @@ VkResult anv_AllocateMemory(
*/
if (image->needs_set_tiling) {
const uint32_t i915_tiling =
isl_tiling_to_i915_tiling(image->planes[0].surface.isl.tiling);
isl_tiling_to_i915_tiling(image->planes[0].primary_surface.isl.tiling);
int ret = anv_gem_set_tiling(device, mem->bo->gem_handle,
image->planes[0].surface.isl.row_pitch_B,
image->planes[0].primary_surface.isl.row_pitch_B,
i915_tiling);
if (ret) {
anv_device_release_bo(device, mem->bo);

20
src/intel/vulkan/anv_image.c
View File

@@ -413,11 +413,11 @@ add_aux_surface_if_supported(struct anv_device *device,
return VK_SUCCESS;
ok = isl_surf_get_hiz_surf(&device->isl_dev,
&image->planes[plane].surface.isl,
&image->planes[plane].primary_surface.isl,
&image->planes[plane].aux_surface.isl);
assert(ok);
if (!isl_surf_supports_ccs(&device->isl_dev,
&image->planes[plane].surface.isl)) {
&image->planes[plane].primary_surface.isl)) {
image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ;
} else if (image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT) &&
@@ -443,7 +443,7 @@ add_aux_surface_if_supported(struct anv_device *device,
return VK_SUCCESS;
if (!isl_surf_supports_ccs(&device->isl_dev,
&image->planes[plane].surface.isl))
&image->planes[plane].primary_surface.isl))
return VK_SUCCESS;
image->planes[plane].aux_usage = ISL_AUX_USAGE_STC_CCS;
@@ -493,7 +493,7 @@ add_aux_surface_if_supported(struct anv_device *device,
return VK_SUCCESS;
ok = isl_surf_get_ccs_surf(&device->isl_dev,
&image->planes[plane].surface.isl,
&image->planes[plane].primary_surface.isl,
&image->planes[plane].aux_surface.isl,
NULL, 0);
if (!ok)
@@ -532,7 +532,7 @@ add_aux_surface_if_supported(struct anv_device *device,
} else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && image->samples > 1) {
assert(!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT));
ok = isl_surf_get_mcs_surf(&device->isl_dev,
&image->planes[plane].surface.isl,
&image->planes[plane].primary_surface.isl,
&image->planes[plane].aux_surface.isl);
if (!ok)
return VK_SUCCESS;
@@ -595,7 +595,7 @@ add_primary_surface(struct anv_device *device,
{
bool ok;
struct anv_surface *anv_surf = &image->planes[plane].surface;
struct anv_surface *anv_surf = &image->planes[plane].primary_surface;
ok = isl_surf_init(&device->isl_dev, &anv_surf->isl,
.dim = vk_to_isl_surf_dim[image->type],
@@ -636,7 +636,7 @@ check_surfaces(const struct anv_image *image,
* to the aux's offset.
*/
uintmax_t plane_end = plane->offset + plane->size;
const struct anv_surface *primary_surface = &plane->surface;
const struct anv_surface *primary_surface = &plane->primary_surface;
const struct anv_surface *aux_surface = &plane->aux_surface;
uintmax_t last_surface_offset = MAX2(primary_surface->offset, aux_surface->offset);
uintmax_t last_surface_size = aux_surface->isl.size_B > 0
@@ -1174,7 +1174,7 @@ void anv_GetImageSubresourceLayout(
} else {
uint32_t plane = anv_image_aspect_to_plane(image->aspects,
subresource->aspectMask);
surface = &image->planes[plane].surface;
surface = &image->planes[plane].primary_surface;
}
assert(__builtin_popcount(subresource->aspectMask) == 1);
@@ -1406,7 +1406,7 @@ anv_layout_to_aux_state(const struct gen_device_info * const devinfo,
assert(aux_usage != ISL_AUX_USAGE_NONE);
/* All images that use an auxiliary surface are required to be tiled. */
assert(image->planes[plane].surface.isl.tiling != ISL_TILING_LINEAR);
assert(image->planes[plane].primary_surface.isl.tiling != ISL_TILING_LINEAR);
/* Handle a few special cases */
switch (layout) {
@@ -1741,7 +1741,7 @@ anv_image_fill_surface_state(struct anv_device *device,
{
uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
const struct anv_surface *surface = &image->planes[plane].surface,
const struct anv_surface *surface = &image->planes[plane].primary_surface,
*aux_surface = &image->planes[plane].aux_surface;
struct isl_view view = *view_in;

2
src/intel/vulkan/anv_private.h
View File

@@ -3819,7 +3819,7 @@ struct anv_image {
VkDeviceSize size;
uint32_t alignment;
struct anv_surface surface;
struct anv_surface primary_surface;
/**
* A surface which shadows the main surface and may have different

28
src/intel/vulkan/genX_cmd_buffer.c
View File

@@ -367,7 +367,7 @@ anv_can_fast_clear_color_view(struct anv_device * device,
* format re-interpretation is for sRGB.
*/
if (isl_color_value_requires_conversion(clear_color,
&iview->image->planes[0].surface.isl,
&iview->image->planes[0].primary_surface.isl,
&iview->planes[0].isl)) {
anv_perf_warn(device, &iview->base,
"Cannot fast-clear to colors which would require "
@@ -426,7 +426,7 @@ anv_can_hiz_clear_ds_view(struct anv_device *device,
VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT,
layout);
if (!blorp_can_hiz_clear_depth(&device->info,
&iview->image->planes[0].surface.isl,
&iview->image->planes[0].primary_surface.isl,
clear_aux_usage,
iview->planes[0].isl.base_level,
iview->planes[0].isl.base_array_layer,
@@ -464,12 +464,12 @@ anv_image_init_aux_tt(struct anv_cmd_buffer *cmd_buffer,
{
uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
const struct anv_surface *surface = &image->planes[plane].surface;
const struct anv_surface *surface = &image->planes[plane].primary_surface;
uint64_t base_address =
anv_address_physical(anv_address_add(image->planes[plane].address,
surface->offset));
const struct isl_surf *isl_surf = &image->planes[plane].surface.isl;
const struct isl_surf *isl_surf = &image->planes[plane].primary_surface.isl;
uint64_t format_bits = gen_aux_map_format_bits_for_isl_surf(isl_surf);
/* We're about to live-update the AUX-TT. We really don't want anyone else
@@ -583,7 +583,7 @@ transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
* largest portion of the specified range as it can. For depth images,
* that means the entire image because we don't support multi-LOD HiZ.
*/
assert(image->planes[0].surface.isl.levels == 1);
assert(image->planes[0].primary_surface.isl.levels == 1);
if (will_full_fast_clear)
return;
@@ -1151,9 +1151,9 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
* we need to ensure the shadow copy is up-to-date.
*/
assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
assert(image->planes[plane].surface.isl.tiling == ISL_TILING_LINEAR);
assert(image->planes[plane].primary_surface.isl.tiling == ISL_TILING_LINEAR);
assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR);
assert(isl_format_is_compressed(image->planes[plane].surface.isl.format));
assert(isl_format_is_compressed(image->planes[plane].primary_surface.isl.format));
assert(plane == 0);
anv_image_copy_to_shadow(cmd_buffer, image,
VK_IMAGE_ASPECT_COLOR_BIT,
@@ -1164,7 +1164,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
if (base_layer >= anv_image_aux_layers(image, aspect, base_level))
return;
assert(image->planes[plane].surface.isl.tiling != ISL_TILING_LINEAR);
assert(image->planes[plane].primary_surface.isl.tiling != ISL_TILING_LINEAR);
if (initial_layout == VK_IMAGE_LAYOUT_UNDEFINED ||
initial_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
@@ -1244,7 +1244,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
}
anv_image_ccs_op(cmd_buffer, image,
image->planes[plane].surface.isl.format,
image->planes[plane].primary_surface.isl.format,
ISL_SWIZZLE_IDENTITY,
aspect, level, base_layer, level_layer_count,
ISL_AUX_OP_AMBIGUATE, NULL, false);
@@ -1270,7 +1270,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
assert(base_level == 0 && level_count == 1);
anv_image_mcs_op(cmd_buffer, image,
image->planes[plane].surface.isl.format,
image->planes[plane].primary_surface.isl.format,
ISL_SWIZZLE_IDENTITY,
aspect, base_layer, layer_count,
ISL_AUX_OP_FAST_CLEAR, NULL, false);
@@ -1358,7 +1358,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
if (image->samples == 1) {
anv_cmd_predicated_ccs_resolve(cmd_buffer, image,
image->planes[plane].surface.isl.format,
image->planes[plane].primary_surface.isl.format,
ISL_SWIZZLE_IDENTITY,
aspect, level, array_layer, resolve_op,
final_fast_clear);
@@ -1372,7 +1372,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
continue;
anv_cmd_predicated_mcs_resolve(cmd_buffer, image,
image->planes[plane].surface.isl.format,
image->planes[plane].primary_surface.isl.format,
ISL_SWIZZLE_IDENTITY,
aspect, array_layer, resolve_op,
final_fast_clear);
@@ -5204,7 +5204,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
if (image && (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
uint32_t depth_plane =
anv_image_aspect_to_plane(image->aspects, VK_IMAGE_ASPECT_DEPTH_BIT);
const struct anv_surface *surface = &image->planes[depth_plane].surface;
const struct anv_surface *surface = &image->planes[depth_plane].primary_surface;
info.depth_surf = &surface->isl;
@@ -5239,7 +5239,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
if (image && (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT)) {
uint32_t stencil_plane =
anv_image_aspect_to_plane(image->aspects, VK_IMAGE_ASPECT_STENCIL_BIT);
const struct anv_surface *surface = &image->planes[stencil_plane].surface;
const struct anv_surface *surface = &image->planes[stencil_plane].primary_surface;
info.stencil_surf = &surface->isl;