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amd/common: Remove redundant code for determining memory ops per clock

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Fixes: 82fd379d9e ("amd/common: move ac_memory_ops_per_clock into ac_gpu_info.h")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18038>
This commit is contained in:
Friedrich Vock
2022-08-12 19:19:47 +02:00
committed by Marge Bot
parent 4291e545d5
commit 50238f4958
4 changed files with 31 additions and 45 deletions
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24
src/amd/common/ac_gpu_info.c
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@@ -906,22 +906,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info)
info->uvd_fw_version = info->ip[AMD_IP_UVD].num_queues ? uvd_version : 0; info->uvd_fw_version = info->ip[AMD_IP_UVD].num_queues ? uvd_version : 0;
info->vce_fw_version = info->ip[AMD_IP_VCE].num_queues ? vce_version : 0; info->vce_fw_version = info->ip[AMD_IP_VCE].num_queues ? vce_version : 0;
/* Based on MemoryOpsPerClockTable from PAL. */ info->memory_freq_mhz_effective *= ac_memory_ops_per_clock(info->vram_type);
switch (info->vram_type) {
case AMDGPU_VRAM_TYPE_DDR2:
case AMDGPU_VRAM_TYPE_DDR3:
case AMDGPU_VRAM_TYPE_DDR4: /* same for LPDDR4 */
case AMDGPU_VRAM_TYPE_HBM: /* same for HBM2 and HBM3 */
info->memory_freq_mhz_effective *= 2;
break;
case AMDGPU_VRAM_TYPE_DDR5: /* same for LPDDR5 */
case AMDGPU_VRAM_TYPE_GDDR5:
info->memory_freq_mhz_effective *= 4;
break;
case AMDGPU_VRAM_TYPE_GDDR6:
info->memory_freq_mhz_effective *= 16;
break;
}
/* unified ring */ /* unified ring */
info->has_video_hw.vcn_decode info->has_video_hw.vcn_decode
@@ -2011,15 +1996,16 @@ void ac_get_task_info(struct radeon_info *info,
uint32_t ac_memory_ops_per_clock(uint32_t vram_type) uint32_t ac_memory_ops_per_clock(uint32_t vram_type)
{ {
/* Based on MemoryOpsPerClockTable from PAL. */
switch (vram_type) { switch (vram_type) {
case AMDGPU_VRAM_TYPE_UNKNOWN: case AMDGPU_VRAM_TYPE_UNKNOWN:
return 0; return 0;
case AMDGPU_VRAM_TYPE_DDR2: case AMDGPU_VRAM_TYPE_DDR2:
case AMDGPU_VRAM_TYPE_DDR3: case AMDGPU_VRAM_TYPE_DDR3:
case AMDGPU_VRAM_TYPE_DDR4: case AMDGPU_VRAM_TYPE_DDR4: /* same for LPDDR4 */
case AMDGPU_VRAM_TYPE_HBM: case AMDGPU_VRAM_TYPE_HBM: /* same for HBM2 and HBM3 */
return 2; return 2;
case AMDGPU_VRAM_TYPE_DDR5: case AMDGPU_VRAM_TYPE_DDR5: /* same for LPDDR5 */
case AMDGPU_VRAM_TYPE_GDDR5: case AMDGPU_VRAM_TYPE_GDDR5:
return 4; return 4;
case AMDGPU_VRAM_TYPE_GDDR6: case AMDGPU_VRAM_TYPE_GDDR6:

15
src/amd/common/ac_gpu_info.h
View File

@@ -33,21 +33,6 @@
#include <stdint.h> #include <stdint.h>
#include <stdio.h> #include <stdio.h>
#ifdef _WIN32
#define AMDGPU_VRAM_TYPE_UNKNOWN 0
#define AMDGPU_VRAM_TYPE_GDDR1 1
#define AMDGPU_VRAM_TYPE_DDR2 2
#define AMDGPU_VRAM_TYPE_GDDR3 3
#define AMDGPU_VRAM_TYPE_GDDR4 4
#define AMDGPU_VRAM_TYPE_GDDR5 5
#define AMDGPU_VRAM_TYPE_HBM 6
#define AMDGPU_VRAM_TYPE_DDR3 7
#define AMDGPU_VRAM_TYPE_DDR4 8
#define AMDGPU_VRAM_TYPE_GDDR6 9
#define AMDGPU_VRAM_TYPE_DDR5 10
#else
#include "drm-uapi/amdgpu_drm.h"
#endif
#include "util/macros.h" #include "util/macros.h"
#ifdef __cplusplus #ifdef __cplusplus

23
src/amd/common/ac_rgp.c
View File

@@ -32,6 +32,7 @@
#include "ac_spm.h" #include "ac_spm.h"
#include "ac_sqtt.h" #include "ac_sqtt.h"
#include "ac_gpu_info.h" #include "ac_gpu_info.h"
#include "amd_family.h"
#include <stdbool.h> #include <stdbool.h>
#include <string.h> #include <string.h>
@@ -366,25 +367,25 @@ static enum sqtt_gfxip_level ac_gfx_level_to_sqtt_gfxip_level(enum amd_gfx_level
static enum sqtt_memory_type ac_vram_type_to_sqtt_memory_type(uint32_t vram_type) static enum sqtt_memory_type ac_vram_type_to_sqtt_memory_type(uint32_t vram_type)
{ {
switch (vram_type) { switch (vram_type) {
case AMDGPU_VRAM_TYPE_UNKNOWN: case AMD_VRAM_TYPE_UNKNOWN:
return SQTT_MEMORY_TYPE_UNKNOWN; return SQTT_MEMORY_TYPE_UNKNOWN;
case AMDGPU_VRAM_TYPE_DDR2: case AMD_VRAM_TYPE_DDR2:
return SQTT_MEMORY_TYPE_DDR2; return SQTT_MEMORY_TYPE_DDR2;
case AMDGPU_VRAM_TYPE_DDR3: case AMD_VRAM_TYPE_DDR3:
return SQTT_MEMORY_TYPE_DDR3; return SQTT_MEMORY_TYPE_DDR3;
case AMDGPU_VRAM_TYPE_DDR4: case AMD_VRAM_TYPE_DDR4:
return SQTT_MEMORY_TYPE_DDR4; return SQTT_MEMORY_TYPE_DDR4;
case AMDGPU_VRAM_TYPE_GDDR5: case AMD_VRAM_TYPE_GDDR5:
return SQTT_MEMORY_TYPE_GDDR5; return SQTT_MEMORY_TYPE_GDDR5;
case AMDGPU_VRAM_TYPE_HBM: case AMD_VRAM_TYPE_HBM:
return SQTT_MEMORY_TYPE_HBM; return SQTT_MEMORY_TYPE_HBM;
case AMDGPU_VRAM_TYPE_GDDR6: case AMD_VRAM_TYPE_GDDR6:
return SQTT_MEMORY_TYPE_GDDR6; return SQTT_MEMORY_TYPE_GDDR6;
case AMDGPU_VRAM_TYPE_DDR5: case AMD_VRAM_TYPE_DDR5:
return SQTT_MEMORY_TYPE_LPDDR5; return SQTT_MEMORY_TYPE_LPDDR5;
case AMDGPU_VRAM_TYPE_GDDR1: case AMD_VRAM_TYPE_GDDR1:
case AMDGPU_VRAM_TYPE_GDDR3: case AMD_VRAM_TYPE_GDDR3:
case AMDGPU_VRAM_TYPE_GDDR4: case AMD_VRAM_TYPE_GDDR4:
default: default:
unreachable("Invalid vram type"); unreachable("Invalid vram type");
} }

14
src/amd/common/amd_family.h
View File

@@ -171,6 +171,20 @@ enum amd_ip_type
AMD_NUM_IP_TYPES, AMD_NUM_IP_TYPES,
}; };
enum amd_vram_type {
AMD_VRAM_TYPE_UNKNOWN = 0,
AMD_VRAM_TYPE_GDDR1,
AMD_VRAM_TYPE_DDR2,
AMD_VRAM_TYPE_GDDR3,
AMD_VRAM_TYPE_GDDR4,
AMD_VRAM_TYPE_GDDR5,
AMD_VRAM_TYPE_HBM,
AMD_VRAM_TYPE_DDR3,
AMD_VRAM_TYPE_DDR4,
AMD_VRAM_TYPE_GDDR6,
AMD_VRAM_TYPE_DDR5,
};
const char *ac_get_family_name(enum radeon_family family); const char *ac_get_family_name(enum radeon_family family);
#ifdef __cplusplus #ifdef __cplusplus