diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index bb1bcd65f78..37c8cff0415 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -906,22 +906,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info) info->uvd_fw_version = info->ip[AMD_IP_UVD].num_queues ? uvd_version : 0; info->vce_fw_version = info->ip[AMD_IP_VCE].num_queues ? vce_version : 0; - /* Based on MemoryOpsPerClockTable from PAL. */ - switch (info->vram_type) { - case AMDGPU_VRAM_TYPE_DDR2: - case AMDGPU_VRAM_TYPE_DDR3: - case AMDGPU_VRAM_TYPE_DDR4: /* same for LPDDR4 */ - case AMDGPU_VRAM_TYPE_HBM: /* same for HBM2 and HBM3 */ - info->memory_freq_mhz_effective *= 2; - break; - case AMDGPU_VRAM_TYPE_DDR5: /* same for LPDDR5 */ - case AMDGPU_VRAM_TYPE_GDDR5: - info->memory_freq_mhz_effective *= 4; - break; - case AMDGPU_VRAM_TYPE_GDDR6: - info->memory_freq_mhz_effective *= 16; - break; - } + info->memory_freq_mhz_effective *= ac_memory_ops_per_clock(info->vram_type); /* unified ring */ info->has_video_hw.vcn_decode @@ -2011,15 +1996,16 @@ void ac_get_task_info(struct radeon_info *info, uint32_t ac_memory_ops_per_clock(uint32_t vram_type) { + /* Based on MemoryOpsPerClockTable from PAL. */ switch (vram_type) { case AMDGPU_VRAM_TYPE_UNKNOWN: return 0; case AMDGPU_VRAM_TYPE_DDR2: case AMDGPU_VRAM_TYPE_DDR3: - case AMDGPU_VRAM_TYPE_DDR4: - case AMDGPU_VRAM_TYPE_HBM: + case AMDGPU_VRAM_TYPE_DDR4: /* same for LPDDR4 */ + case AMDGPU_VRAM_TYPE_HBM: /* same for HBM2 and HBM3 */ return 2; - case AMDGPU_VRAM_TYPE_DDR5: + case AMDGPU_VRAM_TYPE_DDR5: /* same for LPDDR5 */ case AMDGPU_VRAM_TYPE_GDDR5: return 4; case AMDGPU_VRAM_TYPE_GDDR6: diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index e89c4ebe2ea..4d34297ceb4 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -33,21 +33,6 @@ #include #include -#ifdef _WIN32 -#define AMDGPU_VRAM_TYPE_UNKNOWN 0 -#define AMDGPU_VRAM_TYPE_GDDR1 1 -#define AMDGPU_VRAM_TYPE_DDR2 2 -#define AMDGPU_VRAM_TYPE_GDDR3 3 -#define AMDGPU_VRAM_TYPE_GDDR4 4 -#define AMDGPU_VRAM_TYPE_GDDR5 5 -#define AMDGPU_VRAM_TYPE_HBM 6 -#define AMDGPU_VRAM_TYPE_DDR3 7 -#define AMDGPU_VRAM_TYPE_DDR4 8 -#define AMDGPU_VRAM_TYPE_GDDR6 9 -#define AMDGPU_VRAM_TYPE_DDR5 10 -#else -#include "drm-uapi/amdgpu_drm.h" -#endif #include "util/macros.h" #ifdef __cplusplus diff --git a/src/amd/common/ac_rgp.c b/src/amd/common/ac_rgp.c index 12bc05fe347..9321a03b5f3 100644 --- a/src/amd/common/ac_rgp.c +++ b/src/amd/common/ac_rgp.c @@ -32,6 +32,7 @@ #include "ac_spm.h" #include "ac_sqtt.h" #include "ac_gpu_info.h" +#include "amd_family.h" #include #include @@ -366,25 +367,25 @@ static enum sqtt_gfxip_level ac_gfx_level_to_sqtt_gfxip_level(enum amd_gfx_level static enum sqtt_memory_type ac_vram_type_to_sqtt_memory_type(uint32_t vram_type) { switch (vram_type) { - case AMDGPU_VRAM_TYPE_UNKNOWN: + case AMD_VRAM_TYPE_UNKNOWN: return SQTT_MEMORY_TYPE_UNKNOWN; - case AMDGPU_VRAM_TYPE_DDR2: + case AMD_VRAM_TYPE_DDR2: return SQTT_MEMORY_TYPE_DDR2; - case AMDGPU_VRAM_TYPE_DDR3: + case AMD_VRAM_TYPE_DDR3: return SQTT_MEMORY_TYPE_DDR3; - case AMDGPU_VRAM_TYPE_DDR4: + case AMD_VRAM_TYPE_DDR4: return SQTT_MEMORY_TYPE_DDR4; - case AMDGPU_VRAM_TYPE_GDDR5: + case AMD_VRAM_TYPE_GDDR5: return SQTT_MEMORY_TYPE_GDDR5; - case AMDGPU_VRAM_TYPE_HBM: + case AMD_VRAM_TYPE_HBM: return SQTT_MEMORY_TYPE_HBM; - case AMDGPU_VRAM_TYPE_GDDR6: + case AMD_VRAM_TYPE_GDDR6: return SQTT_MEMORY_TYPE_GDDR6; - case AMDGPU_VRAM_TYPE_DDR5: + case AMD_VRAM_TYPE_DDR5: return SQTT_MEMORY_TYPE_LPDDR5; - case AMDGPU_VRAM_TYPE_GDDR1: - case AMDGPU_VRAM_TYPE_GDDR3: - case AMDGPU_VRAM_TYPE_GDDR4: + case AMD_VRAM_TYPE_GDDR1: + case AMD_VRAM_TYPE_GDDR3: + case AMD_VRAM_TYPE_GDDR4: default: unreachable("Invalid vram type"); } diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h index 5048ba012ba..67e6ee26234 100644 --- a/src/amd/common/amd_family.h +++ b/src/amd/common/amd_family.h @@ -171,6 +171,20 @@ enum amd_ip_type AMD_NUM_IP_TYPES, }; +enum amd_vram_type { + AMD_VRAM_TYPE_UNKNOWN = 0, + AMD_VRAM_TYPE_GDDR1, + AMD_VRAM_TYPE_DDR2, + AMD_VRAM_TYPE_GDDR3, + AMD_VRAM_TYPE_GDDR4, + AMD_VRAM_TYPE_GDDR5, + AMD_VRAM_TYPE_HBM, + AMD_VRAM_TYPE_DDR3, + AMD_VRAM_TYPE_DDR4, + AMD_VRAM_TYPE_GDDR6, + AMD_VRAM_TYPE_DDR5, +}; + const char *ac_get_family_name(enum radeon_family family); #ifdef __cplusplus