nv50: add PIPELINE_STATISTICS query support, based on nvc0
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Tested-by: Nick Tenney <nick.tenney@gmail.com>
This commit is contained in:
@@ -47,7 +47,7 @@ Note: some of the new features are only available with certain drivers.
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<li>GL_AMD_pinned_memory on r600, radeonsi</li>
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<li>GL_ARB_draw_instanced on freedreno</li>
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<li>GL_ARB_instanced_arrays on freedreno</li>
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<li>GL_ARB_pipeline_statistics_query on i965, nvc0, r600, radeonsi, softpipe</li>
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<li>GL_ARB_pipeline_statistics_query on i965, nv50, nvc0, r600, radeonsi, softpipe</li>
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</ul>
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<h2>Bug fixes</h2>
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@@ -48,7 +48,7 @@ struct nv50_query {
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struct nouveau_mm_allocation *mm;
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};
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#define NV50_QUERY_ALLOC_SPACE 128
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#define NV50_QUERY_ALLOC_SPACE 256
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static INLINE struct nv50_query *
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nv50_query(struct pipe_query *pipe)
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@@ -184,6 +184,16 @@ nv50_query_begin(struct pipe_context *pipe, struct pipe_query *pq)
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nv50_query_get(push, q, 0x20, 0x05805002);
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nv50_query_get(push, q, 0x30, 0x06805002);
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break;
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case PIPE_QUERY_PIPELINE_STATISTICS:
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nv50_query_get(push, q, 0x80, 0x00801002); /* VFETCH, VERTICES */
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nv50_query_get(push, q, 0x90, 0x01801002); /* VFETCH, PRIMS */
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nv50_query_get(push, q, 0xa0, 0x02802002); /* VP, LAUNCHES */
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nv50_query_get(push, q, 0xb0, 0x03806002); /* GP, LAUNCHES */
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nv50_query_get(push, q, 0xc0, 0x04806002); /* GP, PRIMS_OUT */
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nv50_query_get(push, q, 0xd0, 0x07804002); /* RAST, PRIMS_IN */
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nv50_query_get(push, q, 0xe0, 0x08804002); /* RAST, PRIMS_OUT */
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nv50_query_get(push, q, 0xf0, 0x0980a002); /* ROP, PIXELS */
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break;
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case PIPE_QUERY_TIME_ELAPSED:
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nv50_query_get(push, q, 0x10, 0x00005002);
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break;
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@@ -217,6 +227,16 @@ nv50_query_end(struct pipe_context *pipe, struct pipe_query *pq)
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nv50_query_get(push, q, 0x00, 0x05805002);
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nv50_query_get(push, q, 0x10, 0x06805002);
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break;
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case PIPE_QUERY_PIPELINE_STATISTICS:
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nv50_query_get(push, q, 0x00, 0x00801002); /* VFETCH, VERTICES */
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nv50_query_get(push, q, 0x10, 0x01801002); /* VFETCH, PRIMS */
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nv50_query_get(push, q, 0x20, 0x02802002); /* VP, LAUNCHES */
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nv50_query_get(push, q, 0x30, 0x03806002); /* GP, LAUNCHES */
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nv50_query_get(push, q, 0x40, 0x04806002); /* GP, PRIMS_OUT */
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nv50_query_get(push, q, 0x50, 0x07804002); /* RAST, PRIMS_IN */
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nv50_query_get(push, q, 0x60, 0x08804002); /* RAST, PRIMS_OUT */
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nv50_query_get(push, q, 0x70, 0x0980a002); /* ROP, PIXELS */
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break;
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case PIPE_QUERY_TIMESTAMP:
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q->sequence++;
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/* fall through */
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@@ -257,6 +277,7 @@ nv50_query_result(struct pipe_context *pipe, struct pipe_query *pq,
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uint32_t *res32 = (uint32_t *)result;
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boolean *res8 = (boolean *)result;
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uint64_t *data64 = (uint64_t *)q->data;
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int i;
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if (!q->ready) /* update ? */
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q->ready = nv50_query_ready(q);
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@@ -289,6 +310,10 @@ nv50_query_result(struct pipe_context *pipe, struct pipe_query *pq,
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res64[0] = data64[0] - data64[4];
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res64[1] = data64[2] - data64[6];
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break;
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case PIPE_QUERY_PIPELINE_STATISTICS:
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for (i = 0; i < 8; ++i)
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res64[i] = data64[i * 2] - data64[16 + i * 2];
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break;
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case PIPE_QUERY_TIMESTAMP:
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res64[0] = data64[1];
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break;
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@@ -175,6 +175,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
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case PIPE_CAP_CLIP_HALFZ:
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case PIPE_CAP_POLYGON_OFFSET_CLAMP:
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case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
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return 1;
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case PIPE_CAP_SEAMLESS_CUBE_MAP:
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return 1; /* class_3d >= NVA0_3D_CLASS; */
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@@ -198,7 +199,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
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case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
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case PIPE_CAP_TGSI_TEXCOORD:
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case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
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case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
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case PIPE_CAP_TEXTURE_GATHER_SM5:
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case PIPE_CAP_FAKE_SW_MSAA:
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