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intel/brw: Fix SSBO/shared load offset register size for Xe2

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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29273>
This commit is contained in:
Jordan Justen
2023-04-13 15:15:01 -07:00
committed by Marge Bot
parent 4bc4da01f4
commit 4ffe1a9f9e
1 changed files with 2 additions and 1 deletions
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3
src/intel/compiler/brw_fs_nir.cpp
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@@ -6559,7 +6559,8 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb,
const nir_src load_offset = is_ssbo ? instr->src[1] : instr->src[0];
if (nir_src_is_const(load_offset)) {
fs_reg addr = ubld8.MOV(brw_imm_ud(nir_src_as_uint(load_offset)));
const fs_builder &ubld = devinfo->ver >= 20 ? ubld16 : ubld8;
fs_reg addr = ubld.MOV(brw_imm_ud(nir_src_as_uint(load_offset)));
srcs[SURFACE_LOGICAL_SRC_ADDRESS] = component(addr, 0);
} else {
srcs[SURFACE_LOGICAL_SRC_ADDRESS] =