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radv: fix DCC decompress on GFX11

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The hardware requires one color output to be set by CB registers,
otherwise the DCC decompression does nothing.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8127
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8175
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8370
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21629>
This commit is contained in:
Samuel Pitoiset
2023-03-01 09:37:29 +01:00
committed by Marge Bot
parent 57ab623f0b
commit 4ec6850210
1 changed files with 5 additions and 1 deletions
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6
src/amd/vulkan/radv_pipeline.c
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@@ -5066,9 +5066,13 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
* GFX10 supports pixel shaders without exports by setting both the
* color and Z formats to SPI_SHADER_ZERO. The hw will skip export
* instructions if any are present.
*
* GFX11 requires one color output, otherwise the DCC decompression does nothing.
*/
pipeline->need_null_export_workaround =
(device->physical_device->rad_info.gfx_level <= GFX9 || ps->info.ps.can_discard) &&
(device->physical_device->rad_info.gfx_level <= GFX9 || ps->info.ps.can_discard ||
(extra && extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS_GFX11 &&
device->physical_device->rad_info.gfx_level >= GFX11)) &&
!ps->info.ps.writes_z && !ps->info.ps.writes_stencil && !ps->info.ps.writes_sample_mask;
if (pipeline->need_null_export_workaround && !blend.spi_shader_col_format) {
blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;