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intel/nir/fs: replace COMPUTE || KERNEL by gl_shader_stage_is_compute()

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13171>
This commit is contained in:
Lionel Landwerlin
2021-10-18 15:24:23 +03:00
committed by Marge Bot
parent e9ff6f4f06
commit 4ec5da7270
2 changed files with 3 additions and 4 deletions
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4
src/intel/compiler/brw_fs.cpp
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@@ -8940,7 +8940,7 @@ fs_visitor::allocate_registers(bool allow_spilling)
prog_data->total_scratch = MAX2(brw_get_scratch_size(last_scratch),
prog_data->total_scratch);
if (stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL) {
if (gl_shader_stage_is_compute(stage)) {
if (devinfo->platform == INTEL_PLATFORM_HSW) {
/* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
* field documentation, Haswell supports a minimum of 2kB of
@@ -9304,7 +9304,7 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
bool
fs_visitor::run_cs(bool allow_spilling)
{
assert(stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL);
assert(gl_shader_stage_is_compute(stage));
setup_cs_payload();

3
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -108,8 +108,7 @@ fs_visitor::nir_setup_uniforms()
uniforms = nir->num_uniforms / 4;
if ((stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL) &&
devinfo->verx10 < 125) {
if (gl_shader_stage_is_compute(stage) && devinfo->verx10 < 125) {
/* Add uniforms for builtins after regular NIR uniforms. */
assert(uniforms == prog_data->nr_params);