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intel/fs/gen12: Fixup/simplify SWSB annotations of SIMD32 scratch writes.

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Found by inspection.  Existing code was trying to avoid assuming that
an SBID had been assigned to the virtual instruction, but
synchronizing the header setup with respect to the previous SIMD16
SEND by using SYNC.ALLRD doesn't really seem possible unless the SEND
instruction had been assigned an SBID.  Assert-fail instead if no SBID
has been allocated.

Fixes: 15e3a0d9d2 "intel/eu/gen12: Set SWSB annotations in hand-crafted assembly."
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
This commit is contained in:
Francisco Jerez
2020-01-23 22:27:21 -08:00
parent a8ac0bd759
commit 4e4e8d793f
1 changed files with 3 additions and 7 deletions
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10
src/intel/compiler/brw_fs_generator.cpp
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@@ -1378,8 +1378,8 @@ fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
brw_set_default_group(p, inst->group + lower_size * i);
if (i > 0) {
brw_set_default_swsb(p, tgl_swsb_null());
brw_SYNC(p, TGL_SYNC_ALLRD);
assert(swsb.mode & TGL_SBID_SET);
brw_set_default_swsb(p, tgl_swsb_sbid(TGL_SBID_SRC, swsb.sbid));
} else {
brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
}
@@ -1387,11 +1387,7 @@ fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
brw_MOV(p, brw_uvec_mrf(lower_size, inst->base_mrf + 1, 0),
retype(offset(src, block_size * i), BRW_REGISTER_TYPE_UD));
if (i + 1 < inst->exec_size / lower_size)
brw_set_default_swsb(p, tgl_swsb_regdist(1));
else
brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
block_size,
inst->offset + block_size * REG_SIZE * i);