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anv: emit timestamp & availability using the same part of CS

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We've run into issues before where PIPE_CONTROL races MI_STORE_*
commands. So make sure we emit the availability using the same type of
CS so that memory writes are properly ordered.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14552>
This commit is contained in:
Lionel Landwerlin
2022-01-14 10:04:48 +02:00
committed by Marge Bot
parent 730a294b90
commit 4e30da7874
1 changed files with 19 additions and 2 deletions
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21
src/intel/vulkan/genX_query.c
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@@ -725,7 +725,6 @@ void genX(CmdResetQueryPool)(
switch (pool->type) { switch (pool->type) {
case VK_QUERY_TYPE_OCCLUSION: case VK_QUERY_TYPE_OCCLUSION:
case VK_QUERY_TYPE_TIMESTAMP:
for (uint32_t i = 0; i < queryCount; i++) { for (uint32_t i = 0; i < queryCount; i++) {
emit_query_pc_availability(cmd_buffer, emit_query_pc_availability(cmd_buffer,
anv_query_address(pool, firstQuery + i), anv_query_address(pool, firstQuery + i),
@@ -733,6 +732,23 @@ void genX(CmdResetQueryPool)(
} }
break; break;
case VK_QUERY_TYPE_TIMESTAMP: {
for (uint32_t i = 0; i < queryCount; i++) {
emit_query_pc_availability(cmd_buffer,
anv_query_address(pool, firstQuery + i),
false);
}
/* Add a CS stall here to make sure the PIPE_CONTROL above has
* completed. Otherwise some timestamps written later with MI_STORE_*
* commands might race with the PIPE_CONTROL in the loop above.
*/
anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_CS_STALL_BIT,
"vkCmdResetQueryPool of timestamps");
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
break;
}
case VK_QUERY_TYPE_PIPELINE_STATISTICS: case VK_QUERY_TYPE_PIPELINE_STATISTICS:
case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT: { case VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT: {
struct mi_builder b; struct mi_builder b;
@@ -1246,6 +1262,7 @@ void genX(CmdWriteTimestamp2KHR)(
if (stage == VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR) { if (stage == VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR) {
mi_store(&b, mi_mem64(anv_address_add(query_addr, 8)), mi_store(&b, mi_mem64(anv_address_add(query_addr, 8)),
mi_reg64(TIMESTAMP)); mi_reg64(TIMESTAMP));
emit_query_mi_availability(&b, query_addr, true);
} else { } else {
/* Everything else is bottom-of-pipe */ /* Everything else is bottom-of-pipe */
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT; cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
@@ -1259,9 +1276,9 @@ void genX(CmdWriteTimestamp2KHR)(
if (GFX_VER == 9 && cmd_buffer->device->info.gt == 4) if (GFX_VER == 9 && cmd_buffer->device->info.gt == 4)
pc.CommandStreamerStallEnable = true; pc.CommandStreamerStallEnable = true;
} }
emit_query_pc_availability(cmd_buffer, query_addr, true);
} }
emit_query_pc_availability(cmd_buffer, query_addr, true);
/* When multiview is active the spec requires that N consecutive query /* When multiview is active the spec requires that N consecutive query
* indices are used, where N is the number of active views in the subpass. * indices are used, where N is the number of active views in the subpass.