From 4e272003b17af9c5d9b78e3e31176b89b1b20e7b Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Sun, 20 Dec 2020 09:58:45 -0800 Subject: [PATCH] freedreno/ir3: Clean up instruction creation Convert everything remaining over to the version which takes # of register (src + dst) and drop the ir3_instr_create2() version. Signed-off-by: Rob Clark Part-of: --- src/freedreno/ir3/ir3.c | 12 ++------ src/freedreno/ir3/ir3.h | 43 ++++++++++++++++------------ src/freedreno/ir3/ir3_a6xx.c | 2 +- src/freedreno/ir3/ir3_compiler_nir.c | 7 ++--- src/freedreno/ir3/ir3_context.c | 8 +++--- src/freedreno/ir3/ir3_legalize.c | 6 ++-- src/freedreno/ir3/ir3_parser.y | 2 +- src/freedreno/ir3/tests/delay.c | 4 +-- 8 files changed, 41 insertions(+), 43 deletions(-) diff --git a/src/freedreno/ir3/ir3.c b/src/freedreno/ir3/ir3.c index 879ffa4950e..411cd9e8e2c 100644 --- a/src/freedreno/ir3/ir3.c +++ b/src/freedreno/ir3/ir3.c @@ -232,7 +232,7 @@ static int emit_cat2(struct ir3_instruction *instr, void *ptr, { struct ir3_register *dst = instr->regs[0]; struct ir3_register *src1 = instr->regs[1]; - struct ir3_register *src2 = instr->regs[2]; + struct ir3_register *src2 = (instr->regs_count > 2) ? instr->regs[2] : NULL; instr_cat2_t *cat2 = ptr; unsigned absneg = ir3_cat2_absneg(instr->opc); @@ -1141,7 +1141,7 @@ static struct ir3_instruction *instr_create(struct ir3_block *block, int nreg) return instr; } -struct ir3_instruction * ir3_instr_create2(struct ir3_block *block, +struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc, int nreg) { struct ir3_instruction *instr = instr_create(block, nreg); @@ -1151,14 +1151,6 @@ struct ir3_instruction * ir3_instr_create2(struct ir3_block *block, return instr; } -struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc) -{ - /* NOTE: we could be slightly more clever, at least for non-meta, - * and choose # of regs based on category. - */ - return ir3_instr_create2(block, opc, 4); -} - struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr) { struct ir3_instruction *new_instr = instr_create(instr->block, diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h index 8f3df782042..10847089d44 100644 --- a/src/freedreno/ir3/ir3.h +++ b/src/freedreno/ir3/ir3.h @@ -580,8 +580,7 @@ void * ir3_alloc(struct ir3 *shader, int sz); struct ir3_block * ir3_block_create(struct ir3 *shader); -struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc); -struct ir3_instruction * ir3_instr_create2(struct ir3_block *block, +struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc, int nreg); struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr); void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep); @@ -1386,7 +1385,7 @@ create_immed_typed(struct ir3_block *block, uint32_t val, type_t type) struct ir3_instruction *mov; unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0; - mov = ir3_instr_create(block, OPC_MOV); + mov = ir3_instr_create(block, OPC_MOV, 2); mov->cat1.src_type = type; mov->cat1.dst_type = type; __ssa_dst(mov)->flags |= flags; @@ -1407,7 +1406,7 @@ create_uniform_typed(struct ir3_block *block, unsigned n, type_t type) struct ir3_instruction *mov; unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0; - mov = ir3_instr_create(block, OPC_MOV); + mov = ir3_instr_create(block, OPC_MOV, 2); mov->cat1.src_type = type; mov->cat1.dst_type = type; __ssa_dst(mov)->flags |= flags; @@ -1428,7 +1427,7 @@ create_uniform_indirect(struct ir3_block *block, int n, type_t type, { struct ir3_instruction *mov; - mov = ir3_instr_create(block, OPC_MOV); + mov = ir3_instr_create(block, OPC_MOV, 2); mov->cat1.src_type = type; mov->cat1.dst_type = type; __ssa_dst(mov); @@ -1442,7 +1441,7 @@ create_uniform_indirect(struct ir3_block *block, int n, type_t type, static inline struct ir3_instruction * ir3_MOV(struct ir3_block *block, struct ir3_instruction *src, type_t type) { - struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV); + struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV, 2); unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0; __ssa_dst(instr)->flags |= flags; @@ -1462,7 +1461,7 @@ static inline struct ir3_instruction * ir3_COV(struct ir3_block *block, struct ir3_instruction *src, type_t src_type, type_t dst_type) { - struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV); + struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV, 2); unsigned dst_flags = (type_size(dst_type) < 32) ? IR3_REG_HALF : 0; unsigned src_flags = (type_size(src_type) < 32) ? IR3_REG_HALF : 0; @@ -1479,7 +1478,7 @@ ir3_COV(struct ir3_block *block, struct ir3_instruction *src, static inline struct ir3_instruction * ir3_MOVMSK(struct ir3_block *block, unsigned components) { - struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOVMSK); + struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOVMSK, 1); struct ir3_register *dst = __ssa_dst(instr); dst->flags |= IR3_REG_SHARED; @@ -1490,7 +1489,7 @@ ir3_MOVMSK(struct ir3_block *block, unsigned components) static inline struct ir3_instruction * ir3_NOP(struct ir3_block *block) { - return ir3_instr_create(block, OPC_NOP); + return ir3_instr_create(block, OPC_NOP, 0); } #define IR3_INSTR_0 0 @@ -1500,7 +1499,7 @@ static inline struct ir3_instruction * \ ir3_##name(struct ir3_block *block) \ { \ struct ir3_instruction *instr = \ - ir3_instr_create(block, opc); \ + ir3_instr_create(block, opc, 1); \ instr->flags |= flag; \ return instr; \ } @@ -1513,7 +1512,7 @@ ir3_##name(struct ir3_block *block, \ struct ir3_instruction *a, unsigned aflags) \ { \ struct ir3_instruction *instr = \ - ir3_instr_create(block, opc); \ + ir3_instr_create(block, opc, 2); \ __ssa_dst(instr); \ __ssa_src(instr, a, aflags); \ instr->flags |= flag; \ @@ -1529,7 +1528,7 @@ ir3_##name(struct ir3_block *block, \ struct ir3_instruction *b, unsigned bflags) \ { \ struct ir3_instruction *instr = \ - ir3_instr_create(block, opc); \ + ir3_instr_create(block, opc, 3); \ __ssa_dst(instr); \ __ssa_src(instr, a, aflags); \ __ssa_src(instr, b, bflags); \ @@ -1547,7 +1546,7 @@ ir3_##name(struct ir3_block *block, \ struct ir3_instruction *c, unsigned cflags) \ { \ struct ir3_instruction *instr = \ - ir3_instr_create2(block, opc, 4); \ + ir3_instr_create(block, opc, 4); \ __ssa_dst(instr); \ __ssa_src(instr, a, aflags); \ __ssa_src(instr, b, bflags); \ @@ -1567,7 +1566,7 @@ ir3_##name(struct ir3_block *block, \ struct ir3_instruction *d, unsigned dflags) \ { \ struct ir3_instruction *instr = \ - ir3_instr_create2(block, opc, 5); \ + ir3_instr_create(block, opc, 5); \ __ssa_dst(instr); \ __ssa_src(instr, a, aflags); \ __ssa_src(instr, b, bflags); \ @@ -1684,8 +1683,19 @@ ir3_SAM(struct ir3_block *block, opc_t opc, type_t type, struct ir3_instruction *src0, struct ir3_instruction *src1) { struct ir3_instruction *sam; + unsigned nreg = 1; /* dst */ - sam = ir3_instr_create(block, opc); + if (flags & IR3_INSTR_S2EN) { + nreg++; + } + if (src0) { + nreg++; + } + if (src1) { + nreg++; + } + + sam = ir3_instr_create(block, opc, nreg); sam->flags |= flags; __ssa_dst(sam)->wrmask = wrmask; if (flags & IR3_INSTR_S2EN) { @@ -1763,9 +1773,6 @@ INSTR4F(G, STG) INSTR0(BAR) INSTR0(FENCE) -/* meta instructions: */ -INSTR0(META_TEX_PREFETCH); - /* ************************************************************************* */ #include "regmask.h" diff --git a/src/freedreno/ir3/ir3_a6xx.c b/src/freedreno/ir3/ir3_a6xx.c index b10e1b95027..72d9ba1cff6 100644 --- a/src/freedreno/ir3/ir3_a6xx.c +++ b/src/freedreno/ir3/ir3_a6xx.c @@ -387,7 +387,7 @@ get_atomic_dest_mov(struct ir3_instruction *atomic) return atomic->data; /* We are already out of SSA here, so we can't use the nice builders: */ - mov = ir3_instr_create(atomic->block, OPC_MOV); + mov = ir3_instr_create(atomic->block, OPC_MOV, 2); ir3_reg_create(mov, 0, 0); /* dst */ ir3_reg_create(mov, 0, 0); /* src */ diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index e8dedd40c5d..e7ee1101da4 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -55,7 +55,7 @@ create_input(struct ir3_context *ctx, unsigned compmask) { struct ir3_instruction *in; - in = ir3_instr_create(ctx->in_block, OPC_META_INPUT); + in = ir3_instr_create(ctx->in_block, OPC_META_INPUT, 1); in->input.sysval = ~0; __ssa_dst(in)->wrmask = compmask; @@ -2480,9 +2480,8 @@ emit_tex(struct ir3_context *ctx, nir_tex_instr *tex) compile_assert(ctx, tex->src[idx].src.is_ssa); - sam = ir3_META_TEX_PREFETCH(b); - __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */ - __ssa_src(sam, get_barycentric(ctx, IJ_PERSP_PIXEL), 0); + sam = ir3_SAM(b, opc, type, MASK(ncomp), 0, NULL, + get_barycentric(ctx, IJ_PERSP_PIXEL), 0); sam->prefetch.input_offset = ir3_nir_coord_offset(tex->src[idx].src.ssa); /* make sure not to add irrelevant flags like S2EN */ diff --git a/src/freedreno/ir3/ir3_context.c b/src/freedreno/ir3/ir3_context.c index 8d6418d5b65..ff4cd0e9313 100644 --- a/src/freedreno/ir3/ir3_context.c +++ b/src/freedreno/ir3/ir3_context.c @@ -308,7 +308,7 @@ ir3_create_collect(struct ir3_context *ctx, struct ir3_instruction *const *arr, unsigned flags = dest_flags(arr[0]); - collect = ir3_instr_create2(block, OPC_META_COLLECT, 1 + arrsz); + collect = ir3_instr_create(block, OPC_META_COLLECT, 1 + arrsz); __ssa_dst(collect)->flags |= flags; for (unsigned i = 0; i < arrsz; i++) { struct ir3_instruction *elem = arr[i]; @@ -382,7 +382,7 @@ ir3_split_dest(struct ir3_block *block, struct ir3_instruction **dst, for (int i = 0, j = 0; i < n; i++) { struct ir3_instruction *split = - ir3_instr_create(block, OPC_META_SPLIT); + ir3_instr_create(block, OPC_META_SPLIT, 2); __ssa_dst(split)->flags |= flags; __ssa_src(split, src, flags); split->split.off = i + base; @@ -584,7 +584,7 @@ ir3_create_array_load(struct ir3_context *ctx, struct ir3_array *arr, int n, struct ir3_register *src; unsigned flags = 0; - mov = ir3_instr_create(block, OPC_MOV); + mov = ir3_instr_create(block, OPC_MOV, 2); if (arr->half) { mov->cat1.src_type = TYPE_U16; mov->cat1.dst_type = TYPE_U16; @@ -645,7 +645,7 @@ ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr, int n, return; } - mov = ir3_instr_create(block, OPC_MOV); + mov = ir3_instr_create(block, OPC_MOV, 2); if (arr->half) { mov->cat1.src_type = TYPE_U16; mov->cat1.dst_type = TYPE_U16; diff --git a/src/freedreno/ir3/ir3_legalize.c b/src/freedreno/ir3/ir3_legalize.c index cde28abbec1..9505ff52136 100644 --- a/src/freedreno/ir3/ir3_legalize.c +++ b/src/freedreno/ir3/ir3_legalize.c @@ -297,7 +297,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block) struct ir3_instruction *baryf; /* (ss)bary.f (ei)r63.x, 0, r0.x */ - baryf = ir3_instr_create(block, OPC_BARY_F); + baryf = ir3_instr_create(block, OPC_BARY_F, 3); ir3_reg_create(baryf, regid(63, 0), 0); ir3_reg_create(baryf, 0, IR3_REG_IMMED)->iim_val = 0; ir3_reg_create(baryf, regid(0, 0), 0); @@ -323,7 +323,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block) struct ir3_instruction *baryf; /* (ss)bary.f (ei)r63.x, 0, r0.x */ - baryf = ir3_instr_create(block, OPC_BARY_F); + baryf = ir3_instr_create(block, OPC_BARY_F, 3); ir3_reg_create(baryf, regid(63, 0), 0)->flags |= IR3_REG_EI; ir3_reg_create(baryf, 0, IR3_REG_IMMED)->iim_val = 0; ir3_reg_create(baryf, regid(0, 0), 0); @@ -667,7 +667,7 @@ kill_sched(struct ir3 *ir, struct ir3_shader_variant *so) if (instr->opc != OPC_KILL) continue; - struct ir3_instruction *br = ir3_instr_create(block, OPC_B); + struct ir3_instruction *br = ir3_instr_create(block, OPC_B, 2); br->regs[1] = instr->regs[1]; br->cat0.target = list_last_entry(&ir->block_list, struct ir3_block, node); diff --git a/src/freedreno/ir3/ir3_parser.y b/src/freedreno/ir3/ir3_parser.y index f262563b0f8..f08ef7bb004 100644 --- a/src/freedreno/ir3/ir3_parser.y +++ b/src/freedreno/ir3/ir3_parser.y @@ -79,7 +79,7 @@ int ir3_yyget_lineno(void); static struct ir3_instruction * new_instr(opc_t opc) { - instr = ir3_instr_create(block, opc); + instr = ir3_instr_create(block, opc, 5); instr->flags = iflags.flags; instr->repeat = iflags.repeat; instr->nop = iflags.nop; diff --git a/src/freedreno/ir3/tests/delay.c b/src/freedreno/ir3/tests/delay.c index 6ad2060c7d6..5ffc688c32b 100644 --- a/src/freedreno/ir3/tests/delay.c +++ b/src/freedreno/ir3/tests/delay.c @@ -139,7 +139,7 @@ regs_to_ssa(struct ir3 *ir) unsigned nsrc = 1 + instr->repeat; unsigned flags = src->regs[0]->flags & IR3_REG_HALF; struct ir3_instruction *collect = - ir3_instr_create2(block, OPC_META_COLLECT, 1 + nsrc); + ir3_instr_create(block, OPC_META_COLLECT, 1 + nsrc); __ssa_dst(collect)->flags |= flags; for (unsigned i = 0; i < nsrc; i++) __ssa_src(collect, regfile[regn(reg) + i], flags); @@ -159,7 +159,7 @@ regs_to_ssa(struct ir3 *ir) for (unsigned i = 0; i < ndst; i++) { struct ir3_instruction *split = - ir3_instr_create(block, OPC_META_SPLIT); + ir3_instr_create(block, OPC_META_SPLIT, 2); __ssa_dst(split)->flags |= flags; __ssa_src(split, instr, flags); split->split.off = i;