OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/rt: switch to common pass for shader calls lowering

Browse Source 
v2: rename for new indices

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8637>
This commit is contained in:
Lionel Landwerlin
2021-05-28 15:06:09 +03:00
committed by Marge Bot
parent 1dacea10f3
commit 4d9fcf2799
3 changed files with 62 additions and 1048 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1072
src/intel/compiler/brw_nir_lower_shader_calls.c
View File

File diff suppressed because it is too large Load Diff

5
src/intel/compiler/brw_nir_rt.h
View File

@@ -51,10 +51,7 @@ void brw_nir_lower_combined_intersection_any_hit(nir_shader *intersection,
void brw_nir_lower_shader_returns(nir_shader *shader); void brw_nir_lower_shader_returns(nir_shader *shader);
bool brw_nir_lower_shader_calls(nir_shader *shader, bool brw_nir_lower_shader_calls(nir_shader *shader);
nir_shader ***resume_shaders_out,
uint32_t *num_resume_shaders_out,
void *mem_ctx);
void brw_nir_lower_rt_intrinsics(nir_shader *shader, void brw_nir_lower_rt_intrinsics(nir_shader *shader,
const struct intel_device_info *devinfo); const struct intel_device_info *devinfo);

11
src/intel/vulkan/anv_pipeline.c
View File

@@ -2479,13 +2479,18 @@ compile_upload_rt_shader(struct anv_ray_tracing_pipeline *pipeline,
nir_shader **resume_shaders = NULL; nir_shader **resume_shaders = NULL;
uint32_t num_resume_shaders = 0; uint32_t num_resume_shaders = 0;
if (nir->info.stage != MESA_SHADER_COMPUTE) { if (nir->info.stage != MESA_SHADER_COMPUTE) {
NIR_PASS_V(nir, brw_nir_lower_shader_calls, NIR_PASS_V(nir, nir_lower_shader_calls,
nir_address_format_64bit_global,
BRW_BTD_STACK_ALIGN,
&resume_shaders, &num_resume_shaders, mem_ctx); &resume_shaders, &num_resume_shaders, mem_ctx);
NIR_PASS_V(nir, brw_nir_lower_shader_calls);
NIR_PASS_V(nir, brw_nir_lower_rt_intrinsics, devinfo);
} }
NIR_PASS_V(nir, brw_nir_lower_rt_intrinsics, devinfo); for (unsigned i = 0; i < num_resume_shaders; i++) {
for (unsigned i = 0; i < num_resume_shaders; i++) NIR_PASS_V(resume_shaders[i], brw_nir_lower_shader_calls);
NIR_PASS_V(resume_shaders[i], brw_nir_lower_rt_intrinsics, devinfo); NIR_PASS_V(resume_shaders[i], brw_nir_lower_rt_intrinsics, devinfo);
}
stage->code = stage->code =
brw_compile_bs(compiler, pipeline->base.device, mem_ctx, brw_compile_bs(compiler, pipeline->base.device, mem_ctx,