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aco: implement 64-bit nir_op_ffloor on GFX6

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GFX6 doesn't have V_FLOOR_F64, it needs to be lowered. Loosely based
on the AMDGPU LLVM backend.

Introduce a new function because it will be useful for some other
64-bit operations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3477>
This commit is contained in:
Samuel Pitoiset
2020-01-20 09:00:07 +01:00
parent fbd169e421
commit 4d92601715
1 changed files with 32 additions and 1 deletions
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33
src/amd/compiler/aco_instruction_selection.cpp
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@@ -780,6 +780,37 @@ Temp emit_trunc_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
return bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst_lo, dst_hi); return bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst_lo, dst_hi);
} }
Temp emit_floor_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
{
if (ctx->options->chip_class >= GFX7)
return bld.vop1(aco_opcode::v_floor_f64, Definition(dst), val);
/* GFX6 doesn't support V_FLOOR_F64, lower it. */
Temp src0 = as_vgpr(ctx, val);
Temp mask = bld.copy(bld.def(s1), Operand(3u)); /* isnan */
Temp min_val = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(-1u), Operand(0x3fefffffu));
Temp isnan = bld.vopc_e64(aco_opcode::v_cmp_class_f64, bld.hint_vcc(bld.def(bld.lm)), src0, mask);
Temp fract = bld.vop1(aco_opcode::v_fract_f64, bld.def(v2), src0);
Temp min = bld.vop3(aco_opcode::v_min_f64, bld.def(v2), fract, min_val);
Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), src0);
Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), min);
Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, isnan);
Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, isnan);
Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), dst0, dst1);
Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src0, v);
static_cast<VOP3A_instruction*>(add)->neg[1] = true;
return add->definitions[0].getTemp();
}
void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
{ {
if (!instr->dest.dest.is_ssa) { if (!instr->dest.dest.is_ssa) {
@@ -1689,7 +1720,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
if (dst.size() == 1) { if (dst.size() == 1) {
emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst); emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
} else if (dst.size() == 2) { } else if (dst.size() == 2) {
emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f64, dst); emit_floor_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
} else { } else {
fprintf(stderr, "Unimplemented NIR instr bit size: "); fprintf(stderr, "Unimplemented NIR instr bit size: ");
nir_print_instr(&instr->instr, stderr); nir_print_instr(&instr->instr, stderr);