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anv: Improve brw_nir_lower_mem_access_bit_sizes

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This commit makes us take both bit size and alignment into account so
that we can properly handle cases such as when we have a 32-bit store
to an 8-bit-aligned address.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4367>
This commit is contained in:
Jason Ekstrand
2020-03-26 20:10:40 -05:00
committed by Marge Bot
parent c643979228
commit 4c8b100388
1 changed files with 5 additions and 5 deletions
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10
src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c
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@@ -81,15 +81,15 @@ lower_mem_load_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
intrin->intrinsic == nir_intrinsic_load_scratch;
assert(intrin->dest.is_ssa);
if (intrin->dest.ssa.bit_size == 32 &&
(!needs_scalar || intrin->num_components == 1))
return false;
const unsigned bit_size = intrin->dest.ssa.bit_size;
const unsigned num_components = intrin->dest.ssa.num_components;
const unsigned bytes_read = num_components * (bit_size / 8);
const unsigned align = nir_intrinsic_align(intrin);
if (bit_size == 32 && align >= 32 &&
(!needs_scalar || intrin->num_components == 1))
return false;
nir_ssa_def *result;
nir_src *offset_src = nir_get_io_offset_src(intrin);
if (bit_size < 32 && nir_src_is_const(*offset_src)) {
@@ -167,7 +167,7 @@ lower_mem_store_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
assert(writemask < (1 << num_components));
if ((value->bit_size <= 32 && num_components == 1) ||
(value->bit_size == 32 &&
(value->bit_size == 32 && align >= 32 &&
writemask == (1 << num_components) - 1 &&
!needs_scalar))
return false;