OpenHarmony/third_party_mesa3d
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radeonsi/vcn: enable dbk in avc encoding

Browse Source 
enable deblocking filter in avc encoder.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18992>
This commit is contained in:
Ruijing Dong
2022-10-06 16:37:47 -04:00
committed by Marge Bot
parent afc9f48858
commit 4bcd5ee5b2
3 changed files with 57 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/gallium/drivers/radeonsi/radeon_vcn_enc.c
View File

@@ -92,6 +92,17 @@ static void radeon_vcn_enc_h264_get_cropping_param(struct radeon_encoder *enc,
}
}
static void radeon_vcn_enc_h264_get_dbk_param(struct radeon_encoder *enc,
struct pipe_h264_enc_picture_desc *pic)
{
enc->enc_pic.h264_deblock.disable_deblocking_filter_idc =
CLAMP(pic->dbk.disable_deblocking_filter_idc, 0, 2);
enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = pic->dbk.alpha_c0_offset_div2;
enc->enc_pic.h264_deblock.beta_offset_div2 = pic->dbk.beta_offset_div2;
enc->enc_pic.h264_deblock.cb_qp_offset = pic->pic_ctrl.chroma_qp_index_offset;
enc->enc_pic.h264_deblock.cr_qp_offset = pic->pic_ctrl.second_chroma_qp_index_offset;
}
static void radeon_vcn_enc_h264_get_spec_misc_param(struct radeon_encoder *enc,
struct pipe_h264_enc_picture_desc *pic)
{
@@ -104,6 +115,10 @@ static void radeon_vcn_enc_h264_get_spec_misc_param(struct radeon_encoder *enc,
enc->enc_pic.spec_misc.cabac_init_idc = enc->enc_pic.spec_misc.cabac_enable ?
pic->pic_ctrl.enc_cabac_init_idc : 0;
enc->enc_pic.spec_misc.deblocking_filter_control_present_flag =
pic->pic_ctrl.deblocking_filter_control_present_flag;
enc->enc_pic.spec_misc.redundant_pic_cnt_present_flag =
pic->pic_ctrl.redundant_pic_cnt_present_flag;
}
static void radeon_vcn_enc_h264_get_rc_param(struct radeon_encoder *enc,
@@ -198,6 +213,7 @@ static void radeon_vcn_enc_h264_get_param(struct radeon_encoder *enc,
enc->enc_pic.is_ltr = pic->is_ltr;
enc->enc_pic.ltr_idx = pic->is_ltr ? pic->ltr_index : 0;
radeon_vcn_enc_h264_get_cropping_param(enc, pic);
radeon_vcn_enc_h264_get_dbk_param(enc, pic);
radeon_vcn_enc_h264_get_rc_param(enc, pic);
radeon_vcn_enc_h264_get_spec_misc_param(enc, pic);
radeon_vcn_enc_h264_get_vui_param(enc, pic);

4
src/gallium/drivers/radeonsi/radeon_vcn_enc.h
View File

@@ -226,6 +226,10 @@ typedef struct rvcn_enc_h264_spec_misc_s {
uint32_t level_idc;
uint32_t b_picture_enabled;
uint32_t weighted_bipred_idc;
struct {
uint32_t deblocking_filter_control_present_flag:1;
uint32_t redundant_pic_cnt_present_flag:1;
};
} rvcn_enc_h264_spec_misc_t;
typedef struct rvcn_enc_hevc_spec_misc_s {

49
src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c
View File

@@ -221,12 +221,6 @@ static void radeon_enc_rc_layer_init(struct radeon_encoder *enc)
static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc)
{
enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0;
enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0;
enc->enc_pic.h264_deblock.beta_offset_div2 = 0;
enc->enc_pic.h264_deblock.cb_qp_offset = 0;
enc->enc_pic.h264_deblock.cr_qp_offset = 0;
RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_h264);
RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
@@ -664,18 +658,26 @@ static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_ue(enc, 0x0);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 2);
radeon_enc_code_se(enc, 0x0);
radeon_enc_code_se(enc, 0x0);
radeon_enc_code_se(enc, 0x0);
radeon_enc_code_fixed_bits(enc, 0x1, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* bottom_field_pic_order_in_frame_present_flag */
radeon_enc_code_ue(enc, 0x0); /* num_slice_groups_minus_1 */
radeon_enc_code_ue(enc, 0x0); /* num_ref_idx_l0_default_active_minus1 */
radeon_enc_code_ue(enc, 0x0); /* num_ref_idx_l1_default_active_minus1 */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* weighted_pred_flag */
radeon_enc_code_fixed_bits(enc, 0x0, 2); /* weighted_bipred_idc */
radeon_enc_code_se(enc, 0x0); /* pic_init_qp_minus26 */
radeon_enc_code_se(enc, 0x0); /* pic_init_qs_minus26 */
radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.cb_qp_offset); /* chroma_qp_index_offset */
/* deblocking_filter_control_present_flag */
radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.deblocking_filter_control_present_flag), 1);
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* constrained_intra_pred_flag */
/* redundant_pic_cnt_present_flag */
radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.redundant_pic_cnt_present_flag), 1);
if (enc->enc_pic.spec_misc.redundant_pic_cnt_present_flag) {
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* transform_8x8_mode_flag */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pic_scaling_matrix_present_flag */
/* second_chroma_qp_index_offset */
radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.cr_qp_offset);
}
radeon_enc_code_fixed_bits(enc, 0x1, 1);
@@ -961,11 +963,12 @@ static void radeon_enc_slice_header(struct radeon_encoder *enc)
instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
inst_index++;
radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1 : 0);
if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
if (enc->enc_pic.spec_misc.deblocking_filter_control_present_flag) {
radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
}
}
radeon_enc_flush_headers(enc);