From 4b3243104cd639bbf67a7a68051b5ed35dad50e3 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Wed, 7 Sep 2022 14:09:04 -0700 Subject: [PATCH] intel/fs/xe2+: Update TCS payload setup for Xe2 reg size. Reviewed-by: Caio Oliveira Reviewed-by: Jordan Justen Part-of: --- src/intel/compiler/brw_fs_thread_payload.cpp | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp index b63405cc8fe..1b6ff46deff 100644 --- a/src/intel/compiler/brw_fs_thread_payload.cpp +++ b/src/intel/compiler/brw_fs_thread_payload.cpp @@ -57,16 +57,21 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v) assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH); assert(tcs_key->input_vertices <= BRW_MAX_TCS_INPUT_VERTICES); - patch_urb_output = brw_ud8_grf(1, 0); + unsigned r = 0; - unsigned r = 2; + r += reg_unit(v.devinfo); - if (tcs_prog_data->include_primitive_id) - primitive_id = brw_vec8_grf(r++, 0); + patch_urb_output = brw_ud8_grf(r, 0); + r += reg_unit(v.devinfo); + + if (tcs_prog_data->include_primitive_id) { + primitive_id = brw_vec8_grf(r, 0); + r += reg_unit(v.devinfo); + } /* ICP handles occupy the next 1-32 registers. */ icp_handle_start = brw_ud8_grf(r, 0); - r += brw_tcs_prog_key_input_vertices(tcs_key); + r += brw_tcs_prog_key_input_vertices(tcs_key) * reg_unit(v.devinfo); num_regs = r; }